Non-Volatile Memory and Method With Power-Saving Read and Program-Verify Operations

• US 20070014156A1
• Filed: 09/22/2006
• Published: 01/18/2007
• Est. Priority Date: 03/16/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Seungpil Lee, Siu Chan, Yan Li
• Inventors: Li, Yan, Lee, Seungpil, Chan, Siu
• Granted Patent: US 7,570,513 B2
• Time in Patent Office: Days
• US Class Current: 365/185.170
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification

Abstract

A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.

Claims

1. A non-volatile memory, comprising:

memory cells organized as an array of NAND chains, each NAND chain accessible via a bit line; and

a switch coupled between said each NAND chain and the bit line, said switch responsive to a voltage condition on the bit line to connect said each NAND chain to the bit line when the bit line is substantially at zero voltage and to disconnect said each NAND chain from the bit line when the bit line is substantially at a supply voltage.

2. A non-volatile memory as in claim 1, wherein said switch comprises:

an n-channel transistor having a control gate, said n-channel transistor connected in series between said each NAND chain and the bit line; and

a p-channel transistor having a control gate, said p-channel transistor connected in series between a supply voltage and the control gate of the n-channel, said control gate of the p-channel being connected to the bit line.

3. The method as in any one of claims 1-2, wherein each of said memory cells stores one bit of data.

4. The method as in any one of claims 1-2, wherein each of said memory cells stores more than one bit of data.