Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies

• US 20070014168A1
• Filed: 06/23/2006
• Published: 01/18/2007
• Est. Priority Date: 06/24/2005
• Status: Abandoned Application

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google LLC (Alphabet Inc.)
• Inventors: Rajan, Suresh
• Application Number:
  US11/474,076
• Publication Number:
  US 20070014168A1
• Time in Patent Office: Days
• US Class Current: 365/201
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activating, pre-charging and refreshing operations to the memory cells). The second integrated circuit die comprises a second interface that interfaces the memory core, via the first interface circuit, an external bus, such as a synchronous interface to an external bus. A technique combines memory core integrated circuit dies with interface integrated circuit dies to configure a memory device. A speed test on the memory core integrated circuit dies is conducted, and the interface integrated circuit die is electrically coupled to the memory core integrated circuit die based on the speed of the memory core integrated circuit die.

Claims

1. A method for configuring a memory device, said method comprising:

conducting at least one test on a plurality of memory core integrated circuit dies;

identifying at least one characteristic of said memory core integrated circuit dies from said test; and

electrically coupling an interface integrated circuit die to said memory core integrated circuit die based on said memory core integrated circuit characteristic.

2. A method as set forth in claim 1, wherein identifying at least one characteristic of said memory core integrated circuit die from said test comprises identifying a speed of operation for said memory core integrated circuit die.

3. A method as set forth in claim 2, wherein:

identifying a speed of operation for said memory core integrated circuit comprises identifying at least one memory core integrated circuit die that operates at a slow speed relative to operation of other memory core integrated circuit dies; and

electrically coupling an interface integrated circuit die to said memory core integrated circuit die comprises coupling an interface integrated circuit die, designed for low power markets, to said memory core integrated circuit die that operates at a relatively slow speed.

4. A method as set forth in claim 2, wherein:

identifying a speed of operation for said memory core integrated circuit comprises identifying at least one memory core integrated circuit die that operates at a high speed relative to operation of other memory core integrated circuit dies; and

electrically coupling an interface integrated circuit die to said memory core integrated circuit die comprises coupling an interface integrated circuit die, designed for high performance markets, to said memory core integrated circuit die that operates at a high speed.

5. A method as set forth in claim 2, wherein:

identifying a speed of operation for said memory core integrated circuit comprises identifying at least one memory core integrated circuit die that operates at an average speed relative to operation of other memory core integrated circuit dies; and

electrically coupling an interface integrated circuit die to said memory core integrated circuit die comprises coupling an interface integrated circuit die, designed for power conservation and performance markets, to said memory core integrated circuit die that operates at an average speed.

6. The method as set forth in claim 1, wherein conducting at least one test on a plurality of memory core integrated circuit dies comprises conducting a speed test to measure the amount of time required for a read, write, activate, pre-charge, or refresh operations.

7. The method as set forth in claim 1, wherein:

conducting at least one test on a plurality of memory core integrated circuit dies comprises conducting a test to determine if a memory core integrated circuit die comprises defective rows or columns;

identifying at least one characteristic of said memory core integrated circuit dies from said test comprises identifying at least one non-defective memory core integrated circuit die that does not contain any defective rows or columns; and

electrically coupling an interface integrated circuit die to said memory core integrated circuit die comprises electrically coupling an interface integrated circuit die, designed for high performance markets, to said non-defective memory core integrated circuit die.

8. A method for configuring a memory device, said method comprising:

conducting at least one test on a plurality of memory core integrated circuit dies to characterize said memory core integrated circuit dies based on speed of operation;

configuring an effective data rate for an interface on said memory core integrated circuit die based on said speed of operation of said memory core integrated circuit die; and

electrically coupling an interface integrated circuit die to said memory core integrated circuit die to operate with an external bus and to operate in conjunction with said effective data rate of said interface on said memory core integrated circuit die.

9. A method as set forth in claim 8, wherein:

conducting at least one test on a plurality of memory core integrated circuit dies to characterize said memory core integrated circuit dies comprises characterizing at least one memory core integrated circuit die as a slow memory core integrated circuit die;

configuring an effective data rate for an interface on said memory core integrated circuit die comprises configuring a relatively high data rate for an interface on said memory core integrated circuit die; and

electrically coupling an interface integrated circuit die to said memory core integrated circuit die comprises electrically coupling an interface integrated circuit die that operates at said relatively high data rate.

10. A method as set forth in claim 8, wherein:

conducting at least one test on a plurality of memory core integrated circuit dies to characterize said memory core integrated circuit dies comprises characterizing at least one memory core integrated circuit die as a slow memory core integrated circuit die;

configuring an effective data rate for an interface on said memory core integrated circuit die comprises configuring a relatively medium speed data rate for an interface on said memory core integrated circuit die; and

electrically coupling an interface integrated circuit die to said memory core integrated circuit die comprises electrically coupling an interface integrated circuit die to said external bus that operates at said medium speed data rate.

11. A memory device comprising:

first integrated circuit die comprising;

memory core comprising a plurality of memory cells, said memory cell comprising an access time for executing operations on said memory cells;

first interface circuit coupled to said memory cells, comprising an internal data rate, corresponding to said access time, for transferring data between said memory cells and said first interface circuit; and

second integrated circuit die, electrically coupled to said first integrated circuit die, comprising a second interface comprising an external data rate for accessing data, at a data rate from said first interface circuit compatible with said internal data rate of said first interface circuit, and for interfacing said data to an external circuit.

12. A memory device as set forth in claim 11, wherein said access time of said memory cells comprises a relatively slow access time, said internal data rate comprises a relatively high data rate, and said external data rate comprises a relatively high data rate.

13. A memory device as set forth in claim 11, wherein said access time of said memory cells comprises a relatively slow access time, said internal data rate comprises a an average data rate, and said external data rate comprises an average data rate.