Semiconductor memory device, and method of controlling the same

• US 20070014178A1
• Filed: 09/06/2006
• Published: 01/18/2007
• Est. Priority Date: 11/09/1999
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Fujioka, Shinya, Sato, Kotoku, Nishimura, Koichi, Kawakubo, Tomohiro
• Granted Patent: US 7,483,323 B2
• Time in Patent Office: Days
• US Class Current: 365/227
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/3268 Power saving in hard disk drive
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 2211/4067 Refresh in standby or low power modes
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

Claims

1-6. -6. (canceled)

7. A method of controlling a dynamic random access memory including dynamic memory cells, the memory having a low power consumption mode, in which the dynamic memory cells do not retain data therein by prohibiting refresh operations, and an idle mode, comprising the steps of:

providing a first command to the memory for entering the idle mode; and

providing a second command to the memory during the idle mode for entering the low power consumption mode.

8. The method of controlling the dynamic random access memory according to claim 7,

wherein the memory enters the low power consumption mode in response to a voltage change of one control signal as the second command.

9. The method of controlling the dynamic random access memory according to claim 8, wherein the memory maintains the low power consumption mode while the control signal keeps a first level.

10. The method of controlling the dynamic random access memory according to claim 7 or 8, wherein the second command comprises a combination of control signals.

11. The method of controlling the dynamic random access memory according to claim 7, further comprising the step of:

providing a third command to the memory for exiting from the low power consumption mode.

12. The method of controlling the dynamic random access memory according to claim 11,

wherein the memory enters the low power consumption mode in response to a voltage change of one control signal as the second command, and the memory exits the low power consumption mode in response to a reverse voltage change of the control signal.

13. The method of controlling the dynamic random access memory according to claim 11, wherein the memory is initialized after the exit from the low power consumption mode.

14. The method of controlling the dynamic random access memory according to claim 13, wherein the memory enters the idle mode after an initialization period during which the memory is initialized.

15. The method of controlling the dynamic random access memory according to claim 7, wherein the dynamic random access memory is one of SDRAM, DDR SDRAM and FCRAM.

16. The method of controlling the dynamic random access memory according to claim 7, wherein the dynamic random access memory is equipped with a cellular phone.