Active rectifier with load impedance switching

• US 20070014374A1
• Filed: 06/29/2006
• Published: 01/18/2007
• Est. Priority Date: 05/29/2003
• Status: Active Grant

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Teridian Semiconductor Corp. (Analog Devices, Inc.)
• Inventors: Hershbarger, Russell
• Granted Patent: US 7,936,830 B2
• Time in Patent Office: Days
• US Class Current: 375/258
• CPC Class Codes: H04L 25/0266 Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching
• CPC Class Codes: H04L 25/493 by transition coding, i.e. the time-position or direction of a transition being encoded before transmission

Abstract

Active rectification with load impedance switching for communication across a pulse transformer is presented. Load impedance switching is used for communicating data from the secondary side of the transformer to the primary side during data frames. During power frames, the load impedance is switched to a capacitor for the storage of charge from received power pulses, which may then be converted into a power source. The active rectifier circuit is configurable to accommodate different power requirements and transformer characteristics, and may be implemented with half-wave or full-wave configurations. In active mode, switches are enabled to short out diodes such that diode voltage losses are overcome in the recovered power supply voltage.

Claims

1. A direct access arrangement with an active rectifier circuit and load impedance switching comprising:

an isolation barrier having a primary side and a secondary side;

a first circuit coupled to said primary side of said isolation barrier, said first circuit configured to communicate a transmit bit-stream from said primary side of said isolation barrier to said secondary side; and

a second circuit coupled to said secondary side of said isolation barrier, said second circuit including an active rectifier circuit and a switchable load impedance circuit, wherein said load impedance circuit is configured for communication of a receive bit-stream from said secondary side to said primary side of said isolation barrier.

2. The direct access arrangement of claim 1, wherein said isolation barrier is a pulse transformer.

3. The direct access arrangement of claim 2, wherein said pulse transformer is a 1:

1 ratio transformer.

4. The direct access arrangement of claim 1, wherein said transmit bit-stream comprises:

a data mode having a first voltage level; and

a power mode having a second voltage level.

5. The direct access arrangement of claim 4, wherein said second voltage level is much greater than said first voltage level.

6. The direct access arrangement of claim 4, wherein said transmit bit-stream is double DC-balance encoded.

7. The direct access arrangement of claim 1, wherein said load impedance circuit is dynamically configurable between three modes comprising:

a first load impedance mode wherein said load impedance is infinite;

a second load impedance mode indicating a value of one for said receive bit-stream; and

a third load impedance mode indicating a value of zero for said receive bit-stream.

8. The direct access arrangement of claim 7, wherein said first load impedance mode is controlled by said active rectifier.

9. The direct access arrangement of claim 3, wherein said active rectifier is a full wave rectifier.

10. The direct access arrangement of claim 2, wherein said pulse transformer is a 1:

2 ratio transformer.

11. The direct access arrangement of claim 10, wherein said active rectifier is a half wave rectifier.

12. The direct access arrangement of claim 4, wherein said active rectifier is activated upon detection of said power mode.

13. The direct access arrangement of claim 12, wherein a one-shot drives said active rectifier upon detection of said power mode.

14. The direct access arrangement of claim 1, wherein a clock signal drives said active rectifier upon recovery of a clock of said transmit bit-stream.

15. The direct access arrangement of claim 4, wherein upon detection of said power mode, said active rectifier is driven in two stages comprising:

using a one-shot to drive said active rectifier while a clock of said transmit bit-stream is recovered by a clock recovery circuit; and

using said recovered clock signal to drive said active rectifier.

16. An apparatus with active rectification and load impedance switching comprising:

an isolation barrier having a primary side and a secondary side;

a first circuit coupled to said primary side of said isolation barrier, said first circuit comprising a voltage driver configured to communicate a transmit bit-stream from said primary side to said secondary side; and

a second circuit coupled to said secondary side of said isolation barrier, said second circuit comprising an active rectifier circuit and a load impedance circuit with dynamic configurability, wherein said configurability is based upon information in said transmit bit-stream and a receive bit-stream that is simultaneously communicated from said secondary side to said primary side.

17. The apparatus of claim 16, wherein said information in said transmit bit-stream comprises power pulses and data pulses.

18. The apparatus of claim 16, wherein said transmit bit-stream is double DC-balance encoded.

19. The apparatus of claim 16, wherein said dynamic configurability comprises:

a first load impedance mode wherein said load impedance is infinite;

a second load impedance mode indicating a value of one for said receive bit-stream; and

a third load impedance mode indicating a value of zero for said receive bit-stream.

20. An apparatus with active rectification and load impedance switching comprising:

a pulse transformer having a primary side and a secondary side, wherein said pulse transformer has a fixed winding ratio between said primary and said secondary;

a voltage driver circuit coupled to said primary side, said voltage driver circuit configured to communicate a transmit bit-stream from said primary side to said secondary side;

an active rectifier circuit coupled to said secondary side of said pulse transformer for recovery of power transmitted from said primary side, wherein said active rectifier circuit is configured based on said fixed winding ratio; and

a load impedance circuit coupled to said active rectifier and said secondary side of said transformer, wherein said load impedance circuit is dynamically configurable to modulate a load current on said primary side based on a receive bit-stream from said secondary side to provide a high impedance state for efficient recovery of said power transmitted from said primary side.