System and method for enhancing read performance of a memory storage system including fully buffered dual in-line memory modules

• US 20070016718A1
• Filed: 06/24/2005
• Published: 01/18/2007
• Est. Priority Date: 06/24/2005
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Radhakrishnan, Ramesh, Pankratz, James
• Granted Patent: US 7,404,057 B2
• Time in Patent Office: Days
• US Class Current: 711/5
• CPC Class Codes: G06F 11/1658 Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence

Abstract

A system and method for enhanced read performance of a memory storage system is disclosed. The storage system includes a first memory controller. At least one first channel of a plurality of memory modules couples to the first memory controller. At least one memory module in the at least one first channel can return data sought in a read request, if present, to the first memory controller without sending the data through each memory module in the at least one first channel. The storage system also includes a second memory controller coupled to at least one second channel of a plurality of memory modules. At least one memory module in the at least one second channel can return data sought in a read request, if present, to the second memory controller without sending the data through each memory module in the at least one second channel. The at least one second channel contains an inverse mirror copy of data stored on the first channel.

Claims

1. A memory storage system, wherein the memory storage system comprises:

a first memory controller,

at least one first channel of a plurality of memory modules coupled to the first memory controller, wherein at least one memory module in the at least one first channel can return data sought in a read request, if present, to the first memory controller without sending the data through each memory module in the at least one first channel,

a second memory controller, and

at least one second channel of a plurality of memory modules coupled to the second memory controller, wherein at least one memory module in the at least one second channel can return data sought in a read request, if present, to the second memory controller without sending the data through each memory module in the at least one second channel, and wherein the second channel contains an inverse mirror copy of data stored on the at least one first channel.

2. The memory storage system of claim 1, wherein each memory module in the at least one first channel can return data sought in a read request, if present, to the first memory controller without sending the data through each memory module in the at least one first channel.

3. The memory storage system of claim 1, wherein each memory module in the at least one second channel can return data sought in a read request, if present, to the second memory controller without sending the data through each memory module in the at least one second channel.

4. The memory storage system of claim 1, wherein each memory module except the last memory module in the at least one first channel can return data sought in a read request, if present, to the first memory controller without sending the data through each memory module in the at least one first channel.

5. The memory storage system of claim 1, wherein each memory module except the last memory module in the at least one second channel can return data sought in a read request, if present, to the second memory controller without sending the data through each memory module in the at least one second channel.

6. The memory storage system of claim 1, wherein each memory module can return data sought in a read request, if present, to a memory controller without sending the data through each memory module in the channel containing the memory module.

7. The memory storage system of claim 1, further comprising:

a third memory controller,

at least one third channel of a plurality of memory modules coupled to the third memory controller, wherein at least one memory module in the third channel can return data sought in a read request, if present, to the third memory controller without sending the data through each memory module in the third channel,

a fourth memory controller,

at least one fourth channel of a plurality of memory modules coupled to the fourth memory controller, wherein at least one memory module in the fourth channel can return data sought in a read request, if present, to the fourth memory controller without sending the data through each memory module in the fourth channel, and wherein the fourth channel contains an inverse mirror copy of data stored on the third channel.

8. The memory storage system of claim 1, further comprising a host coupled to the first and second memory controllers, wherein the host can transmit read requests to the first and second memory controllers.

9. The memory storage system of claim 8, wherein the host can compare information received from the first and second controllers in response to read requests and determine whether the information in the first or second channels is corrupted.

10. A memory storage system, wherein the memory storage system comprises:

a host,

a first memory controller coupled to the host,

a first channel of a plurality fully buffered dual in-line memory modules coupled to the first memory controller, wherein at least one first fully buffered dual in-line memory module in the first channel can return data sought in a read request, if present, to the first memory controller without sending the data through each fully buffered dual in-line memory module in the first channel,

a second memory controller coupled to the host, and

a second channel of a plurality of fully buffered dual in-line memory modules coupled to the second memory controller, wherein at least one fully buffered dual in-line memory module in the second channel can return data sought in a read request, if present, to the second memory controller without sending the data through each fully buffered dual in-line memory module in the second channel, and wherein the second channel contains an inverse mirror copy of data stored on the first channel.

11. The memory storage system of claim 10, wherein each fully buffered dual in-line memory module in the first channel can return data sought in a read request, if present, to the first memory controller without sending the data through each fully buffered dual in-line memory module in the first channel.

12. The memory storage system of claim 10, wherein each fully buffered dual in-line memory module in the second channel can return data sought in a read request, if present, to the second memory controller without sending the data through each fully buffered dual in-line memory module in the second channel.

13. The memory storage system of claim 10, wherein each fully buffered dual in-line memory module except the last fully buffered dual in-line memory module in the first channel can return data sought in a read request, if present, to the first memory controller without sending the data through each fully buffered dual in-line memory module in the first channel.

14. The memory storage system of claim 10, wherein each fully buffered dual in-line memory module except the last fully buffered dual in-line memory module in the second channel can return data sought in a read request, if present, to the second memory controller without sending the data through each fully buffered dual in-line memory module in the second channel.

15. The memory storage system of claim 10, wherein the first and second memory controllers can transmit information received from the first and second channels in response to a read request to the host.

16. The memory storage system of claim 15, wherein the host can compare information received from the first and second controllers and determine whether the information in the first or second channels is corrupted.

17. A method for enhancing read performance of a memory storage system including at least one first channel of a plurality of fully buffered dual in-line memory modules coupled to a first memory controller and at least one second channel of a plurality of fully buffered dual in-line memory modules coupled to a second memory controller, wherein the at least one second channel stores an inverse mirror copy of data stored in the at least one first channel, comprising the steps of:

transmitting a read request substantially simultaneously from the first memory controller to a first fully buffered in-line memory module in the at least one first channel and from the second memory controller to a first fully buffered in-line memory module in the at least one second channels,

determining whether information sought by the read request is available in the first fully buffered in-line memory modules,

returning the information, if found, to the memory controller coupled to the first fully buffered dual in-line memory module containing the information without sending the information to a second fully buffered dual in-line memory module in that channel, and

sending the read request to the second fully buffered in-line memory module in each channel, if the information is not found in the first fully buffered dual in-line memory module in that channel.

18. The method of claim 17, further comprising the step of:

determining whether information sought by the read request is available in the second fully buffered in-line memory module in either channel,

returning the information, if found, to the memory controller coupled to the fully buffered dual in-line memory module containing the information without sending the information through each fully buffered dual in-line memory module in the channel,

sending the read request to successive additional fully buffered in-line memory modules in the channel, if the information is not found in the second fully buffered dual in-line memory module that channel, until the information is found.

19. The method of claim 17, further comprising the step of comparing information received from the first memory controller with information received from the second memory controller in response to a read request to determine whether the information is corrupted.

20. The method of claim 18, further comprising the step of stopping use of information received from the first and second memory controllers if the information is corrupted.