Memory controller based (DE)compression

• US 20070016724A1
• Filed: 06/24/2005
• Published: 01/18/2007
• Est. Priority Date: 06/24/2005
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Herrell, Russ, Gaither, Blaine, Veazey, Judson
• Granted Patent: US 8,473,673 B2
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 2212/401 Compressed data

Abstract

Systems, methodologies, media, and other embodiments associated with (de)compressing data at a time and in a location that facilitates increasing memory transfer bandwidth by selectively controlling a burst-mode protocol used to transfer data to and/or from a memory are described. One exemplary system embodiment includes a memory controller configured to (de)compress memory, to manipulate size data associated with compressed data, and to selectively manipulate a burst-mode protocol employed in transferring compressed data to and/or from random access memory.

Claims

1. A system, comprising:

a memory controller configured;

to receive an uncompressed data block to be stored in memory;

to compress in hardware the uncompressed data block into a compressed data block;

to compute a size of the compressed data block; and

to selectively manipulate a burst-mode protocol employed in communicating data with a random access memory (RAM);

and

a RAM controller operably connected to the memory controller by a bus and to the RAM by a memory interface, the RAM controller being configured;

to receive the compressed data block and the size of the compressed data block from the memory controller;

to write the compressed data block to the RAM via the memory interface using the burst-mode protocol, where the number of bursts required to write the compressed data block to the RAM is controllable by the RAM controller and is based, at least in part, on the size of the compressed data block, and where the compressed data block is written as one or more sub-blocks of data that are aligned on a default burst mode RAM line boundary based, at least in part, on the size of the uncompressed data block; and

to store the size of the compressed data block so that it may be acquired upon a read access targeted at the compressed data block written to the RAM.

2. The system of claim 1, the compressed data block being provided by the memory controller to the RAM controller via the bus, the number of bus cycles employed in providing the compressed data block to the RAM controller being calculated from and controlled, at least in part, by the size of the compressed data block.

3. The system of claim 1, the size of the compressed data block being provided to the RAM controller explicitly as a value.

4. The system of claim 1, the size of the compressed data block being provided to the RAM controller implicitly as an end-of-data marker.

5. The system of claim 1, the RAM controller being configured to store the size of the compressed data block in the RAM explicitly as a value.

6. The system of claim 1, the RAM controller being configured to store the size of the compressed data block in the RAM implicitly as an end-of-data marker.

7. The system of claim 1, the memory controller being configured to store the size of the compressed data block.

8. The system of claim 1, where selectively manipulating the burst-mode protocol includes determining one or more of, an RAS/CAS (row address selection/column address selection) sequence, and a configurable data bit burst length.

9. The system of claim 1, the uncompressed data block being received in the memory controller from one or more of, a processor and an input/output logic, the uncompressed data block being accompanied by a memory action request.

10. The system of claim 9, the memory controller being configured to selectively compress the uncompressed data block based, at least in part, on the memory action request.

11. The system of claim 1, the RAM controller being configured to compute a burst-mode control data based, at least in part, on a data width of the memory interface connecting the RAM controller to the RAM, and the size of the compressed data block.

12. The system of claim 1, the uncompressed data block being a cache line.

13. The system of claim 1, the memory controller being further configured to request that a stored block of compressed data be retrieved from the RAM by the RAM controller.

14. The system of claim 13, the RAM controller being configured to retrieve the stored block of compressed data from the RAM via the memory interface using the burst-mode protocol.

15. The system of claim 14, the RAM controller being configured to acquire a retrieval size of the stored block of compressed data.

16. The system of claim 15, the RAM controller being configured to customize the retrieval of the stored block of compressed data via the memory interface and to control the burst-mode protocol based, at least in part, on the retrieval size of the stored block of compressed data.

17. The system of claim 16, where one of, the RAM controller, and the memory controller are further configured to decompress the block of compressed data into a decompressed block of data after the block of compressed data is retrieved from the RAM.

18. The system of claim 17, the block of compressed data being decompressed into the decompressed block of data in hardware associated with one or more of, the RAM controller, and the memory controller.

19. The system of claim 16, the memory controller being configured to receive the block of compressed data from the RAM controller and to decompress the block of compressed data into a decompressed block of data.

20. The system of claim 16, the memory controller being configured to receive the block of compressed data from the RAM controller and to selectively decompress the block of compressed data into a decompressed block of data based, at least in part, on a memory read request received by the memory controller.

21. A system, comprising:

a memory controller configured;

to receive, from one or more of, a processor, an input/output logic, and a cache, an uncompressed data block to be stored in memory, the uncompressed data block being accompanied by a memory action request;

to compress, in hardware, the uncompressed data block into a compressed data block;

to compute a size of the compressed data block; and

to selectively manipulate a burst-mode protocol employed in communicating data with a random access memory (RAM);

and

a RAM controller operably connected to the memory controller by a bus and to the RAM by a memory interface, the RAM controller being configured;

to receive the compressed data block and the size of the compressed data block from the memory controller, the compressed data block being provided by the memory controller to the RAM controller via the bus, where the number of bus cycles employed in providing the compressed data block to the RAM controller is calculated from and controlled, at least in part, by the size of the compressed data block;

to write the compressed data block to the RAM via the memory interface using the burst-mode protocol as one or more sub-blocks of data aligned on one or more default burst-mode RAM line boundaries based on the size of the uncompressed data block, where the number of bursts required to write the compressed data block to the RAM is controllable by the RAM controller and is based, at least in part, on the size of the compressed data block, the number of bursts required to write the compressed data block to the RAM using the burst-mode protocol being less than the number of bursts required to write the uncompressed data block to the RAM using the burst-mode protocol; and

to store the size of the compressed data block so that it may be acquired upon a read access targeted at the compressed data block written to the RAM.

22. A system, comprising:

a memory controller configured;

to receive, from one or more of, a processor, an input/output logic, and a cache, an uncompressed data block to be stored in memory, the uncompressed data block being accompanied by a memory action request;

to compress, in hardware, the uncompressed data block into a compressed data block;

to compute a size of the compressed data block;

to selectively manipulate a burst-mode protocol employed in communicating data with a random access memory (RAM); and

to request that a stored block of compressed data be retrieved from a RAM;

and

a RAM controller operably connected to the memory controller by a bus and to the RAM by a memory interface, the RAM controller being configured;

to receive the compressed data block and the size of the compressed data block from the memory controller, the compressed data block being provided by the memory controller to the RAM controller via the bus, where the number of bus cycles employed in providing the compressed data block to the RAM controller is calculated from and controlled, at least in part, by the size of the compressed data block;

to write the compressed data block to the RAM via the memory interface as one or more sub-blocks of data aligned on one or more default burst-mode RAM line boundaries using the burst-mode protocol, the number of bursts required to write the compressed data block to the RAM being controllable by the RAM controller and being based, at least in part, on the size of the compressed data block, the number of bursts required to write the compressed data block to the RAM using the burst-mode protocol being less than the number of bursts required to write the uncompressed data block to the RAM using the burst-mode protocol;

to store the size of the compressed data block so that it may be acquired upon a read access targeted at the compressed data block written to the RAM;

to retrieve the stored block of compressed data from the RAM using the burst-mode protocol;

to determine a retrieval size of the stored block of compressed data; and

to customize the retrieval of the stored block of compressed data via the memory interface and to control the burst-mode protocol based, at least in part, on the retrieval size of the stored block of compressed data;

the system being configured to decompress the block of compressed data into a decompressed block of data in hardware associated with one or more of, the RAM controller, and the memory controller.

23. A computer configured with the system of claim 22.

24. A method, comprising:

receiving in a memory controller an uncompressed block of data to be stored in a memory;

compressing the uncompressed block of data into a compressed block of data in hardware associated with the memory controller;

providing the compressed block of data to a RAM controller for storage in the memory; and

controlling the RAM controller to selectively manipulate a burst-mode protocol for transferring data to the memory.

25. The method of claim 24, including:

determining a size of the compressed block of data;

writing the compressed block of data to the memory as one or more sub-blocks of data aligned on one or more default burst-mode RAM boundaries using the burst-mode protocol, where the burst-mode protocol is controlled, at least in part, by the size of the compressed block of data; and

storing the determined size of the compressed block of data so that the determined size may be acquired upon a read access targeted at the compressed data block.

26. The method of claim 25, including:

receiving in the memory controller a request to read a block of compressed data stored in the memory;

retrieving a compressed size of the block of compressed data stored in the memory;

retrieving the block of compressed data from the memory using the burst-mode protocol as controlled, at least in part, by the compressed size; and

decompressing, in hardware, the retrieved block of compressed data.

27. A system, comprising:

a memory controller logic, comprising;

a receive logic configured to receive a data line to be stored in a random access memory;

a compression logic operably connected to the receive logic, the compression logic being configured to compress, in hardware, the data line into a compressed data line; and

a write length logic operably connected to the compression logic, the write length logic being configured to determine the size of the compressed data line;

and

a random access memory controller logic operably connected to the memory controller logic and the RAM, comprising;

a burst-mode control logic configured to control a burst-mode protocol employed by the random access memory controller to write the compressed data line on a default burst-mode boundary in the random access memory; and

a write logic operably connected to the burst-mode control logic, the write logic being configured to write the compressed data line to the random access memory.

28. The system of claim 27, the random access memory controller logic comprising:

a read length logic operably connected to the burst-mode control logic, the read length logic being configured to determine the size of a compressed line of data stored in the random access memory; and

a retrieve logic operably connected to the burst-mode logic, the retrieve logic being configured to retrieve the compressed line of data stored in the random access memory.

29. The system of claim 28, comprising:

a decompression logic operably connected to one or more of, the memory controller logic, and the random access memory controller logic, the decompression logic being configured to decompress the compressed line of data after it is retrieved from the random access memory.

30. The system of claim 29, the decompression logic being located in one or more of, the memory controller logic, and the random access memory controller logic, and the decompression logic being configured to selectively decompress the compressed line of data based, at least in part, on a memory read request received by the memory controller logic.

31. A system, comprising:

means for compressing, in hardware, a block of uncompressed data to be stored in a random access memory;

means for decompressing, in hardware, a block of compressed data stored in the random access memory; and

means for controlling a bus and a bus protocol employed in reading compressed data from the random access memory and writing compressed data to the random access memory, where the controlling is based, at least in part, on an amount of compressed data to be transferred between a memory controller and the random access memory, the means for controlling being operably connected to the means for compressing and the means for decompressing.