Surround gate access transistors with grown ultra-thin bodies

• US 20070018206A1
• Filed: 07/06/2005
• Published: 01/25/2007
• Est. Priority Date: 07/06/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard
• Granted Patent: US 7,888,721 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid phase epitaxial growth process to avoid difficulties with forming sub-lithographic structures via etching processes. The body has ultra-thin dimensions and provides controlled short channel effects with reduced need for high doping levels. Buried data/bit lines are formed in an upper surface of a substrate from which the transistors extend. The transistor can be formed asymmetrically or offset with respect to the data/bit lines. The offset provides laterally asymmetric source regions of the transistors. Continuous conductive paths are provided in the data/bit lines which extend adjacent the source regions to provide better conductive characteristics of the data/bit lines, particularly for aggressively scaled processes.

Claims

1. A transistor comprising:

a vertical annular semiconductive transistor body;

a surround gate structure formed around the annular transistor body;

a source region formed adjacent a lower portion of the body; and

a drain region formed adjacent an upper portion of the body such that the transistor defines a field effect transistor.

2. The transistor of claim 1, further comprising a pillar extending within the annular transistor body.

4. The transistor of claim 1, wherein the gate structure comprises a gate dielectric formed around and adjacent the annular transistor body and a gate conductor formed around and overlying the gate dielectric.

5. The transistor of claim 1, wherein the source region is formed asymmetrically biased on at least one side of the annular transistor body.

6. The transistor of claim 5, wherein conduction channels formed with appropriate potentials extend vertically and asymmetrically along the one side of the annular body.

7. The transistor of claim 1, wherein the transistor body comprises a multiple grain region at an upper surface of the body and wherein the drain region is formed at the upper surface.

3. The transistor of claim 3, wherein the pillar comprises dielectric.

8. An access array for memory cells comprising:

a semiconductive substrate;

a plurality of first conductors formed in a first direction along a surface of the substrate;

a plurality of transistors formed on the surface of the substrate so as to be offset from associated first conductors and at least partially connected to the associated first conductors; and

a plurality of second conductors formed in a second direction and electrically connected with associated transistors such that the transistors can be turned on and off by application of appropriate potentials to the second conductors.

9. The access array of claim 8, further comprising a plurality of charge storage devices connected with corresponding transistors such that each charge storage device and the corresponding transistor together define a memory cell of a memory array.

10. The access array of claim 9, wherein a predetermined charge can be provided to or removed from the charge storage devices via the corresponding transistors and associated first and second conductors to effect write operations to the memory cells.

11. The access array of claim 9, wherein the charge storage devices are stacked on top of the corresponding transistors.

12. The access array of claim 8, wherein the transistors comprise a transistor body and source regions are formed adjacent lower regions of the transistor bodies which overlie the associated first conductors and wherein continuous conductive paths are defined extending along the first conductors and adjacent the source regions.

13. The access array of claim 12, wherein drain regions are formed at upper regions of the transistor and wherein the source regions are laterally asymmetric with respect to the transistor bodies due to the offset of the transistors with respect to the associated first conductors such that conduction channels formed by appropriate potentials applied to the first and second conductors are formed laterally asymmetrically in the transistors.

14. The access array of claim 8, wherein each transistor comprises a single crystalline body region, a multiple grain region formed at an upper end of the single crystalline region, a drain region formed in the multiple grain region, and a source region formed at a lower end of the single crystalline region overlapping the corresponding first conductor.

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