Electronic device including discontinuous storage elements

• US 20070018216A1
• Filed: 07/25/2005
• Published: 01/25/2007
• Est. Priority Date: 07/25/2005
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Chindalore, Gowrishankar, Swift, Craig, Ingersoll, Paul
• Granted Patent: US 7,619,270 B2
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/42348 with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
• CPC Class Codes: H01L 29/42352 with the gate at least partly formed in a trench
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An electronic device can include discontinuous storage elements that lie within a trench. The electronic device can include a substrate including a trench that includes a wall and a bottom and extends from a primary surface of the substrate. The electronic device can also include discontinuous storage elements, wherein a portion of the discontinuous storage elements lies at least within the trench. The electronic device can further include a first gate electrode, wherein at least a part of the portion of the discontinuous storage elements lies between the first gate electrode and the wall of the trench. The electronic device can still further include a second gate electrode overlying the first gate electrode and the primary surface of the substrate.

Claims

1. An electronic device comprising:

a substrate including a first trench that includes a wall and a bottom and extends from a primary surface of the substrate;

discontinuous storage elements, wherein a first portion of the discontinuous storage elements lies at least within the first trench;

a first gate electrode, wherein at least a part of the first portion of the discontinuous storage elements lies between the first gate electrode and the wall of the first trench; and

a second gate electrode overlying the first gate electrode and the primary surface of the substrate.

2. The electronic device of claim 1, wherein the first gate electrode has an upper surface that lies below the primary surface of the substrate.

3. The electronic device of claim 2, wherein the second gate electrode extends at least partly into the first trench.

4. The electronic device of claim 2, further comprising a third gate electrode, wherein:

the substrate further includes a second trench that is spaced apart from the first trench, wherein the second trench includes a wall and a bottom and extends from the primary surface of the substrate;

a second portion of the discontinuous storage elements lies at least within the second trench; and

the third gate electrode has an upper surface that lies below the primary surface of the substrate, wherein at least a part of the second portion of the discontinuous storage elements lies between the third gate electrode and the wall of the second trench.

5. The electronic device of claim 4, further comprising:

a first doped region lying within the substrate below the first trench; and

a second doped region lying within the substrate below the second trench.

6. The electronic device of claim 5, further comprising a third doped region lying along the primary surface of the substrate between the first and second trenches.

7. The electronic device of claim 6, wherein the third doped region extends to the walls of the first and second trenches.

8. The electronic device of claim 6, wherein the third doped region is spaced apart from the walls of the first and second trenches.

9. The electronic device of claim 5, further comprising:

a first charge storage region that includes a first discontinuous storage element within the first portion of the discontinuous storage elements, wherein the first discontinuous storage element lies closer to the upper surface of the first gate electrode than the first doped region; and

a second charge storage region that includes a second discontinuous storage element within the second portion of the discontinuous storage elements, wherein the second discontinuous storage element lies closer to the upper surface of the third gate electrode than the second doped region, and wherein the second charge storage region is spaced apart from the first charge storage region.

10. The electronic device of claim 4, wherein the second gate electrode overlies the first gate electrode, the third gate electrode, and a portion of the substrate between the first and second trenches.

11. The electronic device of claim 4, further comprising a fourth gate electrode, wherein:

the second gate electrode overlies the first gate electrode and a first portion of the substrate between the first and second trenches; and

the fourth gate electrode overlies the third gate electrode and a second portion of the substrate between the first and second trenches.

12. The electronic device of claim 1, further comprising:

a first dielectric layer lying along the wall and bottom of the first trench; and

a second dielectric layer lying between the first portion of the discontinuous storage elements and the first gate electrode.

13. The electronic device of claim 1, wherein the discontinuous storage elements comprise silicon nanocrystals or metal nanoclusters.

14. The electronic device of claim 1, further comprising an array, wherein:

the substrate includes a plurality of trenches, including the first trench; and

within the array, the discontinuous storage elements lie within the trenches of the substrate.

15. The electronic device of claim 14, further comprising a first dielectric layer overlying the first gate electrode and comprising an upper surface within the first trench, wherein:

the first portion of the discontinuous storage elements is spaced apart from the primary surface of the substrate; and

substantially none of the discontinuous storage elements overlie the primary surface of the substrate between the trenches within the array.

16. The electronic device of claim 1, wherein from a cross-sectional view, the first gate electrode has a substantially rectangular shape.

17. The electronic device of claim 1, wherein from a cross-sectional view:

the first gate electrode includes portions; and

the portions of the first gate electrode include curved outer surfaces that face each other.

18. An electronic device comprising:

a substrate including a first trench and a second trench that are spaced apart from each other, wherein each of the first and second trenches includes a wall and a bottom and extends from a primary surface of the substrate;

discontinuous storage elements, wherein a first portion of the discontinuous storage elements lies within the first trench, and a second portion of the discontinuous storage elements lies at least within the second trench;

a first gate electrode lying within the first trench and having an upper surface that lies below the primary surface of the substrate, wherein at least a part of the first portion of the discontinuous storage elements lies between the first gate electrode and the wall of the first trench;

a second gate electrode lying within the second trench and having an upper surface that lies below the primary surface of the substrate, wherein at least a part of the second portion of the discontinuous storage elements lies between the second gate electrode and the wall of the second trench; and

a third gate electrode overlying at least one of the first gate electrode or the second gate electrode.

19. The electronic device of claim 18, further comprising:

a first doped region lying within the substrate along the bottom of the first trench;

a second doped region lying within the substrate along the bottom of the second trench; and

a third doped region lying along the primary surface of the substrate between the first and second trenches.

20. An electronic device comprising:

a substrate including a first trench and a second trench that are spaced apart from each other, wherein each of the first and second trenches includes a wall and a bottom and extends from a primary surface of the substrate;

a first doped region lying within the substrate along the bottom of the first trench;

a second doped region lying within the substrate along the bottom of the second trench;

a first dielectric layer lying along the walls and bottoms of the first and second trenches;

discontinuous storage elements, wherein;

a first portion of the discontinuous storage elements lies within the first trench;

a second portion of the discontinuous storage elements lies within the second trench;

the first and second portions of the discontinuous storage elements are spaced apart from the primary surface of the substrate; and

substantially none of the discontinuous storage elements overlie the primary surface of the substrate between the first and second trenches;

a second dielectric layer adjacent to the discontinuous storage elements within the first and second trenches;

a first gate electrode lying within the first trench and having an upper surface that lies below the primary surface of the substrate, wherein at least a part of the first portion of the discontinuous storage elements lies between the first gate electrode and the wall of the first trench;

a second gate electrode lying within the first trench and having an upper surface that lies below the primary surface of the substrate, wherein at least a part of the first portion of the discontinuous storage elements lies between the first gate electrode and the wall of the first trench;

a third dielectric layer including a first portion overlying the first gate electrode within the first trench and a second portion overlying the second gate electrode within the second trench; and

a third gate electrode overlying the third dielectric layer and at least one of the first gate electrode or the second gate electrode, wherein the third gate electrode lies at least partly within the first trench and the second trench.