Electronic device including discontinuous storage elements

• US 20070018222A1
• Filed: 07/25/2005
• Published: 01/25/2007
• Est. Priority Date: 07/25/2005
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Sadd, Michael, Chang, Ko-Min, Chindalore, Gowrishankar, Hong, Cheong, Swift, Craig
• Granted Patent: US 7,582,929 B2
• Time in Patent Office: Days
• US Class Current: 257/301
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An electronic device can include discontinuous storage elements that lie within a trench. In one embodiment, the electronic device can include a substrate having a trench that includes a wall and a bottom. The electronic device can also include a portion of discontinuous storage elements that lie within the trench. The electronic device can also include a first gate electrode, wherein at least one discontinuous storage element lies along the wall of the trench at an elevation between and upper surface of the first gate electrode and a primary surface of the substrate. The electronic device can also include a second gate electrode overlying the first gate electrode and the primary surface of the substrate. In another embodiment, a conductive line can be electrically connected to one or more rows or columns of memory cells, and another conductive line can be more rows or more columns of memory cells.

Claims

1. An electronic device comprising:

a substrate including a first trench that includes a wall and a bottom and extends from a primary surface of the substrate;

discontinuous storage elements, wherein a first portion of discontinuous storage elements lies within the first trench;

a first gate electrode having an upper surface that lies below the primary surface of the substrate, wherein at least a part of the first portion of the discontinuous storage elements lies along the wall of the first trench at an elevation between the upper surface of the first gate electrode and the primary surface; and

a second gate electrode overlying the first gate electrode and the primary surface of the substrate.

2. The electronic device of claim 1, wherein at least a portion of the second gate electrode extends at least partly into the first trench.

3. The electronic device of claim 2, further comprising a third gate electrode, wherein:

the substrate further includes a second trench that is spaced apart from the first trench, wherein the second trench includes a wall and a bottom and extends from that primary surface of the substrate;

a second portion of the discontinuous storage elements lies at least within the second trench; and

the third gate electrode has an upper surface that lies below the primary surface of the substrate, wherein at least a part of the second portion of the discontinuous storage elements lies along the wall of the second trench at an elevation between the upper surface of the third gate electrode and the primary surface.

4. The electronic device of claim 3, further comprising:

a first doped region lying within the substrate below the first trench; and

a second doped region lying within the substrate below the second trench.

5. The electronic device of claim 4, further comprising a third doped region lying along the primary surface of the substrate between the first and second trenches.

6. The electronic device of claim 5, wherein the third doped region extends to the walls of the first and second trenches.

7. The electronic device of claim 5, wherein the third doped region is spaced apart from the walls of the first and second trenches.

8. The electronic device of claim 4, wherein:

a first charge storage region includes a first discontinuous storage element within the first portion of the discontinuous storage elements, wherein the first discontinuous storage element lies closer to the upper surface of the first gate electrode than the first doped region;

a second charge storage region includes a second discontinuous storage element within the first portion of the discontinuous storage elements, wherein the second discontinuous storage element lies closer to the first doped region than the upper surface of the first gate electrode, and wherein the second charge storage region is spaced apart from the first charge storage region;

a third charge storage region includes a third discontinuous storage element within the second portion of the discontinuous storage elements, wherein the third discontinuous storage element lies closer to the upper surface of the third gate electrode than the second doped region; and

a fourth charge storage region includes a fourth discontinuous storage element within the second portion of the discontinuous storage elements, wherein the fourth discontinuous storage element lies closer to the second doped region than the upper surface of the third gate electrode, and wherein the fourth charge storage region is spaced apart from the third charge storage region.

9. The electronic device of claim 3, wherein the second gate electrode overlies the first gate electrode, the third gate electrode, and a portion the substrate between the first and second trenches.

10. The electronic device of claim 3, further comprising a fourth gate electrode spaced apart from the third gate electrode, wherein:

the second gate electrode overlies the first gate electrode and a first portion of the substrate between the first and second trenches; and

the fourth gate electrode overlies the third gate electrode and a second portion of the substrate between the first and second trenches.

11. The electronic device of claim 1, further comprising an array, wherein within the array, the discontinuous storage elements overlie substantially all of the primary surface and along substantially all of the wall of the first trench.

12. The electronic device of claim 1, wherein the discontinuous storage elements comprise silicon nanocrystals or metal nanoclusters.

13. The electronic device of claim 1, wherein from a cross-sectional view, the first gate electrode has a substantially rectangular shape.

14. The electronic device of claim 1, wherein from a cross-sectional view:

the first gate electrode includes portions; and

the portions of the first gate electrode include curved outer surfaces that face each other.

15. An electronic device comprising:

a substrate including a first trench and a second trench that are spaced apart from each other, wherein each of the first and second trenches includes a wall and a bottom and extends from a primary surface of the substrate;

a first doped region lying within the substrate along the bottom of the first trench;

a second doped region lying within the substrate along the bottom of the second trench;

a first dielectric layer lying along the walls and bottoms of the first and second trenches;

discontinuous storage elements, wherein;

a first portion of the discontinuous storage elements lie at least within the first trench;

a second portion of the discontinuous storage elements lie at least within the second trench; and

a third portion of the discontinuous storage elements overlie the primary surface of the substrate, wherein the third portion of the discontinuous storage elements is contiguous with each of the first and second portions of the discontinuous storage elements;

a second dielectric layer adjacent to the discontinuous storage elements within the first and second trenches;

a first gate electrode lying within the first trench and having an upper surface that lies below the primary surface of the substrate, wherein at least a part of the first portion of the discontinuous storage elements lies along the wall of the first trench at an elevation between the upper surface of the first gate electrode and the primary surface;

a second gate electrode lying within the second trench and having an upper surface that lies below the primary surface of the substrate, wherein at least a part of the second portion of the discontinuous storage elements lies along the wall of the second trench at an elevation between the upper surface of the second gate electrode and the primary surface;

a third dielectric layer including a first portion overlying the first gate electrode within the first trench and a second portion overlying the second gate electrode within the second trench; and

a third gate electrode overlying at least one of the first gate electrode or the second gate electrode, wherein the third gate electrode lies at least partly within the first trench and the second trench.

16. An electronic device comprising:

a first set of memory cells oriented substantially along a first direction;

a second set of memory cells oriented substantially along the first direction;

a first conductive line electrically connected to the first set of memory cells, wherein the first conductive line is of a type including a gate line or a bit line; and

a second conductive line electrically connected to the second set of memory cells, wherein;

the second conductive line is of a same type as the first conductive line; and

when compared to the first conductive line, the second conductive line is electrically connected to more sets of memory cells that lie along the first direction.

17. The electronic device of claim 16, wherein:

each memory cell within the first and second sets of memory cells comprises a nonvolatile memory cell that includes a first gate electrode and a second gate electrode;

for each memory cell within the first and second sets of memory cells;

a discontinuous storage element lies between a channel region and the first gate electrode; and

another discontinuous storage element lies between the channel region and the second gate electrode.

18. The electronic device of claim 17, further comprising a third set of memory cells oriented substantially along the first direction wherein:

the first, second, and third sets of memory cells lie within different rows or different columns as compared to one another;

each memory cell within the third set of memory cells comprises a nonvolatile memory cell that includes a first gate electrode and a second gate electrode;

for each memory cell within the third set of memory cells;

a discontinuous storage element lies between a channel region and the first gate electrode; and

another discontinuous storage element lies between the channel region and the second gate electrode;

the first conductive line is a first gate line that is electrically connected to the first gate electrodes of the first set of memory cells; and

the second conductive line is a second gate line that is electrically connected to the second gate electrodes of the second and third sets of memory cells.

19. The electronic device of claim 16, further comprising a third set of memory cells oriented substantially along the first direction, wherein:

the first, second, and third sets of memory cells lie within different rows or different columns as compared to one another;

the first conductive line is a first bit line; and

the second conductive line is a second bit line electrically connected to the second and third sets of memory cells.

20. The electronic device of claim 16, wherein the first direction is associated with a row or a column.