Nonvolatile storage array with continuous control gate employing hot carrier injection programming

• US 20070018232A1
• Filed: 07/25/2005
• Published: 01/25/2007
• Est. Priority Date: 07/25/2005
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Chindalore, Gowrishankar, Hong, Cheong, Swift, Craig
• Granted Patent: US 7,285,819 B2
• Time in Patent Office: Days
• US Class Current: 257/316
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An array of storage cells include a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the trenches where the charge storage stack includes a layer of discontinuous storage elements (DSEs). A control gate overlies the first trench. The control gate may run perpendicular to the trenches and traverse the first and second trenches. In another implementation, the control gate runs parallel with the trenches. The storage cell may include one or more diffusion regions occupying an upper surface of the substrate between the first and second trenches. The diffusion region may reside between first and second control gates that are parallel to the trenches. Alternatively, a pair of diffusion regions may occur on either side of a control gate that is perpendicular to the trenches.

Claims

1. A storage array comprising an array of storage cells wherein at least one of the storage cells comprises;

a first source/drain region underlying a first trench defined in a semiconductor substrate;

a second source/drain region underlying a second trench in the substrate;

a charge storage stack lining the trenches wherein the charge storage stack includes a layer of discontinuous storage elements (DSEs); and

a control gate over at least one of the trenches;

2. The storage array of claim 1, wherein the DSEs include polysilicon nanocrystals.

3. The storage array of claim 2, wherein the control gate comprises a continuous control gate running perpendicular to the first and second trenches and traversing the first and second trenches.

4. The storage array of claim 3, further comprising a first diffusion region on a first side of the control gate and a second diffusion region on a second side of the control gate.

5. The storage array of claim 4, wherein the first and second diffusion regions are equidistant between the first and second trenches.

6. The storage array of claim 4, wherein the first and second diffusion regions are diagonally placed with the first diffusion region is proximal to the first trench and the second diffusion region is proximal to the second trench.

7. The storage array of claim 2, wherein a first control gate comprises a continuous control gate over and running parallel to the first trench and a second control gate comprises a continuous control gate over and running parallel with the second trench.

8. The storage array of claim 7, further comprising a diffusion region in the substrate between the first and second gates.

9. The storage array of claim 8, wherein the diffusion region is located between isolation regions on either side.

10. The storage array of claim 8, wherein the diffusion region runs extends across the array running parallel to the source/drain regions.

11. A method of programming a storage cell in an array of storage cells, comprising:

biasing a first source/drain region underlying a first trench of a storage cell to a drain programming voltage (V_PD), wherein the trench is lined with a layer of discontinuous storage elements (DSEs);

biasing a second source/drain region to 0 V; and

biasing a first control gate overlying the first trench storage cell to a gate programming voltage (V_PG) to program a first bit of the storage cell by injecting charge into a first injection region of the DSEs.

12. The method of claim 11, further comprising biasing a semiconductor layer in which the first and second source/drain regions reside to 0 V.

13. The method of claim 12, wherein biasing the second source/drain region comprises biasing a second source drain region underlying a second trench in the substrate, wherein the second trench is lined with a layer of DSEs.

14. The method of claim 13, wherein biasing the first control gate comprises biasing a continuous control gate running perpendicular to the first and second trenches and traversing the first and second trenches.

15. The method of claim 12, wherein biasing the second source/drain region comprises biasing a diffusion region occupying an upper portion of the substrate between the first trench and a second trench.

16. The method of claim 15, wherein biasing the first control gate comprises biasing a continuous control gate overlying the first trench and running parallel to the first trench.

17. The method of claim 15, wherein biasing the second source/drain regions comprises biasing a first diffusion region occupy an upper portion of the substrate on a first side of the first control gate running perpendicular to the source/drain trenches.

18. The method of claim 17, further comprising programming a second bit of the storage cell by injection charge into a second injection region of the DSEs, including biasing a third source/drain region occupying an upper portion of the substrate on a second side of the first control gate.

19. A programmable storage cell, comprising:

a semiconductor substrate defining first and second trenches running parallel to each other;

first and second source/drain regions underlying the first and second trenches, respectively;

a layer of silicon nanocrystals lining the trenches;

a first control gate overlying the first trench;

a first diffusion region occupying an upper portion of the substrate between the first and second trenches.

20. The storage device of claim 19, wherein the diffusion region extends across an array parallel to the first and second source/drain regions.