Method and apparatus for use in improving linearity of MOSFET's using an accumulated charge sink

• US 20070018247A1
• Filed: 07/10/2006
• Published: 01/25/2007
• Est. Priority Date: 07/11/2005
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Kelly, Dylan, Brindle, Christopher, Imthurn, George, Burgener, Mark, Kemerling, Clint, Welstand, Robert, Stuber, Michael
• Granted Patent: US 7,910,993 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78615 with a body contact
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Claims

1. An accumulated charge control (ACC) floating body MOSFET (ACC MOSFET), adapted to control nonlinear response of the MOSFET when the MOSFET is operated in an accumulated charge regime, comprising:

a) a MOSFET having a floating body, wherein the floating body MOSFET selectively operates in the accumulated charge regime, and wherein accumulated charge is present in the body of the floating body MOSFET when the MOSFET operates in the accumulated charge regime; and

b) an accumulated charge sink (ACS) operatively coupled to the body of the MOSFET, wherein the ACS removes or otherwise controls the accumulated charge in the MOSFET body.

2. The ACC MOSFET of claim 1, wherein the MOSFET includes a gate, drain, source, and a gate oxide layer positioned between the gate and the body, and wherein the MOSFET operates in the accumulated charge regime when the MOSFET is operated in an off-state (non-conducting state), and wherein charge accumulates within the body in a region proximate the gate oxide.

3. The ACC MOSFET of claim 2, wherein the MOSFET body includes a channel region including a gate modulated conductive channel between the source and the drain, and wherein the source, drain and channel have carriers of identical polarity when the MOSFET is operated in an on-state (conducting state), and wherein the MOSFET operates in the accumulated charge regime when the MOSFET is biased to operate in the off-state and when the accumulated charge has a polarity that is opposite to the polarity of the source, drain and channel carriers.

4. The ACC MOSFET of claim 3, wherein the MOSFET comprises an NMOSFET device, and wherein the accumulated charge comprises holes having “

P”

polarity.

5. The ACC MOSFET of claim 3, wherein the MOSFET comprises a PMOSFET device, and wherein the accumulated charge comprises electrons having “

N”

polarity.

6. The ACC MOSFET of claim 4, wherein the MOSFET comprises an enhancement mode NMOSFET device.

7. The ACC MOSFET of claim 4, wherein the MOSFET comprises a depletion mode NMOSFET device.

8. The ACC MOSFET of claim 5, wherein the MOSFET comprises an enhancement mode PMOSFET device.

9. The ACC MOSFET of claim 5, wherein the MOSFET comprises a depletion mode PMOSFET device.

10. The ACC MOSFET of claim 1, wherein the MOSFET is fabricated in a semiconductor-on-insulator technology.

11. The ACC MOSFET of claim 1, wherein the MOSFET is fabricated on a semiconductor-on-sapphire substrate.

12. The ACC MOSFET of claim 10, wherein the semiconductor-on-insulator technology comprises silicon-germanium (SiGe) fabricated on an insulating substrate.

13. The ACC MOSFET of claim 10, wherein the semiconductor-on-insulator technology comprises gallium arsenide (GaAs) fabricated on an insulating substrate.

14. The ACC MOSFET of claim 1, wherein the MOSFET is fabricated in a semiconductor-on-bonded wafer technology.

15. The ACC MOSFET of claim 14, wherein the MOSFET is fabricated on direct silicon bond substrates by bonding and electrically attaching a film of single-crystal silicon onto a base insulating substrate.

16. The ACC MOSFET of claim 1, wherein the MOSFET has an inherent linearity characteristic, and wherein the linearity of the ACC MOSFET is improved by removing or otherwise reducing the accumulated charge from the MOSFET body.

17. The ACC MOSFET of claim 15, wherein the MOSFET produces harmonic distortion and intermodulation (IMD) effects when implemented in a selected circuit, and wherein the improved linearity of the ACC MOSFET achieved by removing or otherwise reducing the accumulated charge also improves the harmonic distortion and IMD effects, and wherein removing or otherwise reducing the accumulated charge also improves power handling and voltage tolerances associated with the ACC MOSFET.

18. The ACC MOSFET of claim 2, wherein the MOSFET has an inherent drain-to-source breakdown voltage (BVDSS) characteristic, and wherein the BVDSS characteristic of the ACC MOSFET is improved by removing or otherwise reducing the accumulated charge from the MOSFET body.

19. The ACC MOSFET of claim 2, wherein the MOSFET has a drain-to-source off-state capacitance (C_off) when operated in the off-state (non-conducting state), and wherein the off-state capacitance (C_off) exhibits improved linearity characteristics by removing or otherwise reducing the accumulated charge from the MOSFET body.

20. The ACC MOSFET of claim 19, wherein the off-state capacitance (C_off) has an inherent magnitude, and wherein the magnitude of the off-state capacitance (C_off) is decreased by removing or otherwise reducing the accumulated charge from the MOSFET body.

21. The ACC MOSFET of claim 19, wherein the off-state capacitance (C_off) varies over time in a presence of a time varying drain-to-source bias voltage (Vds), and wherein the variations of C_off over time are reduced by removing or otherwise reducing the accumulated charge from the MOSFET body.

22. The ACC MOSFET of claim 19, wherein the off-state capacitance (C_off) varies over time as the accumulated charge accumulates in the MOSFET body, and wherein the variations of C_off over time are reduced by removing or otherwise reducing the accumulated charge from the MOSFET body.

23. The ACC MOSFET of claim 1, wherein the ACS has an impedance greater than approximately 10⁶ ohms.

24. The ACC MOSFET of claim 1, wherein the ACS has an impedance less than approximately 10⁶ ohms.

25. The ACC MOSFET of claim 1, wherein the ACC MOSFET has an inherent power handling capability, and wherein the ACC MOSFET is capable of processing input signals having increased power levels by removing or otherwise reducing the accumulated charge from the MOSFET body.

86. An RF switch circuit for switching RF signals, comprising:

a) an RF input port receiving an RF input signal;

b) an RF output port;

c) a switch transistor grouping having a first node coupled to the RF input port and a second node coupled to the RF output port, wherein the switch transistor grouping is controlled by a first switch control signal (C1); and

d) a shunt transistor grouping having a first node coupled to the RF input port and a second node coupled to ground, wherein the shunt transistor grouping is controlled by a second switch control signal (C1x), and wherein the shunt transistor grouping comprises one or more ACC MOSFETs defined by claim 2;

and wherein when the first switch control signal C1 is enabled, the switch transistor grouping is enabled and the shunt transistor grouping is disabled thereby passing the RF input signal through to the RF output port, and wherein when the second switch control signal C1x is enabled, the shunt transistor grouping is enabled while the switch transistor grouping is disabled thereby shunting the RF input signal to ground.

87. The RF switch of claim 86, wherein the switch transistor grouping comprises a single MOSFET, and wherein the shunt transistor grouping comprises a single ACC MOSFET.

88. The RF switch of claim 86, wherein the switch transistor grouping comprises a plurality of MOSFETs arranged in a stacked configuration, and wherein the shunt transistor grouping comprises a plurality of ACC MOSFETs arranged in a stacked configuration.

89. The RF switch of claim 88, wherein the switch transistor grouping comprises a first number of MOSFETs arranged in a stacked configuration, and wherein the shunt transistor grouping comprises a second number of ACC MOSFETs arranged in a stacked configuration, and wherein the first number and the second number differ from one another.

90. The RF switch of claim 86, wherein the ACC MOSFET includes a gate terminal electrically coupled to the gate, a drain terminal electrically coupled to the drain, a source terminal electrically coupled to the source, and an ACS terminal electrically coupled to the ACS, and wherein the gate and ACS terminals are electrically coupled together and also coupled to the second switch control signal C1x, and wherein the accumulated charge is removed from the body of the ACC MOSFET through the ACS and gate terminals.

91. The RF switch of claim 90, wherein the switch transistor grouping comprises a single MOSFET, and wherein the shunt transistor grouping comprises a single ACC MOSFET.

92. The RF switch of claim 90, wherein the switch transistor grouping comprises a plurality of MOSFETs arranged in a stacked configuration, and wherein the shunt transistor grouping comprises a plurality of ACC MOSFETs arranged in a stacked configuration.

93. The RF switch of claim 90, wherein the RF switch exhibits harmonic distortion, intermodulation distortion (IMD) and linearity performance characteristics under operation, and wherein the RF switch is capable of processing RF signals of a selected power level, and wherein the harmonic distortion, IMD, linearity characteristics, and power level processing of the RF switch are improved by removal or control of the accumulated charge from the body of the shunt transistor grouping.

94. The RF switch of claim 93, wherein the harmonic and intermodulation distortion of the RF signal output at the RF output port is reduced or eliminated by the removal or control of the accumulated charge from the body of the shunt transistor grouping.

95. The RF switch of claim 90, wherein a diode is coupled between the gate and ACS terminals such that the diode prevents positive current flow into the ACC MOSFET body when the ACC MOSFET is enabled and the diode is reverse-biased, and wherein the ACS terminal is coupled to the second switch control signal C1x via the diode, and wherein the accumulated charge is removed from the body of the ACC MOSFET through the ACS terminal.

96. The RF switch of claim 95, wherein the switch transistor grouping comprises a single MOSFET, and wherein the shunt transistor grouping comprises a single ACC MOSFET.

98. The RF switch of claim 86, wherein the ACC MOSFET includes a gate terminal electrically coupled to the gate, a drain terminal electrically coupled to the drain, a source terminal electrically coupled to the source, and an ACS terminal electrically coupled to the ACS, and wherein the ACS terminal is electrically coupled to an accumulated charge sinking mechanism, and wherein the sinking mechanism comprises a control circuit adapted to control or remove the accumulated charge from the body when the shunt transistor grouping operates in the accumulated charge regime.

99. The RF switch of claim 98, wherein the switch transistor grouping comprises a single MOSFET, and wherein the shunt transistor grouping comprises a single ACC MOSFET.

100. The RF switch of claim 98, wherein the switch transistor grouping comprises a plurality of MOSFETs arranged in a stacked configuration, and wherein the shunt transistor grouping comprises a plurality of ACC MOSFETs arranged in a stacked configuration.

101. The RF switch of claim 98, wherein the ACS terminal of the shunt transistor grouping is coupled to a third switch control signal (C2), and wherein the shunt transistor grouping is enabled by the second switch control signal C1x while the switch transistor grouping is disabled thereby shunting the RF input signal to ground, and wherein the accumulated charge is removed from the body of the ACC MOSFET when the shunt transistor grouping is disabled.

102. The RF switch of claim 95, wherein the RF switch exhibits harmonic distortion, intermodulation distortion (IMD) and linearity performance characteristics under operation, and wherein the RF switch is capable of processing RF signals of a selected power level, and wherein the harmonic distortion, IMM, linearity characteristics, and power level processing of the RF switch are improved by removal or control of the accumulated charge from the body of the shunt transistor grouping.

103. The RF switch of claim 98, wherein the RF switch exhibits harmonic distortion, intermodulation distortion (IMD) and linearity performance characteristics under operation, and wherein the RF switch is capable of processing RF signals of a selected power level, and wherein the harmonic distortion, IMD, linearity characteristics, and power level processing of the RF switch are improved by removal or control of the accumulated charge from the body of the shunt transistor grouping.

104. The RF switch of claim 90, wherein the switch transistor grouping comprises one or more ACC MOSFETs defined by claim 2.

105. The RF switch of claim 95, wherein the switch transistor grouping comprises one or more ACC MOSFETs defined by claim 2.

106. The RF switch of claim 98, wherein the switch transistor grouping comprises one or more ACC MOSFETs defined by claim 2.

107. The RF switch of claim 90, wherein the RF switch comprises a single-pole, multi-throw switch.

108. The RF switch of claim 95, wherein the RF switch comprises a single-pole, multi-throw switch.

109. The RF switch of claim 98, wherein the RF switch comprises a single-pole, multi-throw switch.

110. The RF switch of claim 90, wherein the RF switch comprises a multi-pole, single-throw switch.

111. The RF switch of claim 95, wherein the RF switch comprises a multi-pole, single-throw switch.

112. The RF switch of claim 98, wherein the RF switch comprises a multi-pole, single-throw switch.

113. The RF switch of claim 90, wherein the RF switch comprises a multi-pole, multi-throw switch.

114. The RF switch of claim 95, wherein the RF switch comprises a multi-pole, multi-throw switch.

115. The RF switch of claim 98, wherein the RF switch comprises a multi-pole, multi-throw switch.

118. The RF switch of claim 90, wherein the ACC MOSFET further includes a drain-to-source resistor (R_ds) electrically coupled between the drain and source of the ACC MOSFET.

119. The RF switch of claim 118, wherein the drain-to-source resistor (R_ds) provides a path between the ACC MOSFET drain and source whereby current associated with controlling the accumulate charge is conducted away from the source and drain when the ACC MOSFET is configured in series with other high impedance elements.

120. The RF switch of claim 119, wherein the gate of the ACC MOSFET is coupled to a gate resistor, and wherein the drain-to-source resistor (R_ds) has an impedance approximately equal to the impedance of the gate resistor.

121. The RF switch of claim 92, wherein the ACC MOSFETs further include a plurality of drain-to-source resistors (R_ds) associated with and respective to each of the stacked ACC MOSFETs, on a one-to-one basis, wherein each of the drain-to-source resistors are electrically coupled between the drain and source of each of their associated and respective ACC MOSFETs, and wherein the gates of each of the respective ACC MOSFETs are coupled to associated and respective gate resistors, and wherein the drain-to-source resistors (R_ds) of each associated and respective ACC MOSFET in the stack has an impedance approximately equal to the impedance of its associated and respective gate resistor divided by a number of ACC MOSFETs in the stack.

122. An RF switch circuit for switching RF signals, comprising:

a) a first input port receiving a first RF input signal (RF1);

b) a second input port receiving a second RF input signal (RF2);

c) an RF common port;

d) a first switch transistor grouping having a first node coupled to the first input port and a second node coupled to the RF common port, wherein the first switch transistor grouping is controlled by a first switch control signal (C1);

e) a second switch transistor grouping having a first node coupled to the second input port and a second node coupled to the RF common port, wherein the second switch transistor grouping is controlled by a second switch control signal (C1x);

f) a first shunt transistor grouping having a first node coupled to the second input port and a second node coupled to ground, wherein the first shunt transistor grouping is controlled by the first switch control signal C1; and

g) a second shunt transistor grouping having a first node coupled to the first input port and a second node coupled to ground, wherein the second shunt transistor grouping is controlled by the second switch control signal C1x;

wherein, when C1 is enabled, the first switch and first shunt transistor groupings are enabled while the second switch and shunt transistor groupings are disabled, thereby passing the first RF input signal RF1 through to the RF common port and shunting the second RF input signal RF2 to ground, and wherein when C1 is disabled and C1x is enabled, the second switch and shunt transistor groupings are enabled while the first switch and shunt transistor groupings are disabled, thereby passing the second RF input signal RF2 through to the RF common port and shunting the first RF input signal RF1 to ground, and wherein the switch and shunt transistor groupings comprise one or more ACC MOSFETs defined by claim 1.

123. The RF switch of claim 122, wherein each of the ACC MOSFETs include an ACS terminal in electrical communication with their respective and associated ACSs, and wherein the ACS terminals of each of the ACC MOSFETs are controlled by a sinking mechanism, and wherein the sinking mechanism removes accumulated charge from the ACC MOSFET bodies when the ACC MOSFETs operate in the accumulated charge regime.

124. The RF switch of claim 123, wherein the RF switch exhibits harmonic distortion, intermodulation distortion (IMD) and linearity performance characteristics under operation, and wherein the RF switch is capable of processing RF signals of a selected power level, and wherein the harmonic distortion, E4D, linearity characteristics, and power level processing of the RF switch are improved by removal or control of the accumulated charge from the bodies of the ACC MOSFETs.

125. The RF switch of claim 123, wherein the ACC MOSFETs inherent drain-to-source breakdown voltage (BVDSS) characteristics, and wherein the BVDSS characteristics of the ACC MOSFETs are improved by removing or otherwise reducing the accumulated charge from the MOSFET bodies.

126. The RF switch of claim 123, wherein the RF switch exhibits small-signal performance characteristics including insertion loss, insertion phase (delay), and isolation, and wherein the small-signal performance characteristics of the RF switch are improved by removal and control of the accumulated charge from the ACC MOSFET bodies.

127. The RF switch of claim 123, wherein the RF switch includes associated temperature performance characteristics, and wherein the temperature performance characteristics of the RF switch are improved by removal and control of the accumulated charge from the ACC MOSFET bodies, and wherein the RF switch also exhibits decreased sensitivity to Vdd and fabrication process variations.

128. The RF switch of claim 122, wherein the RF switch comprises a single-pole, multi-throw switch.

129. The RF switch of claim 122, wherein the RF switch comprises a multi-pole, single-throw switch.

130. The RF switch of claim 122, wherein the RF switch comprises a multi-pole, multi-throw switch.

131. The ACC MOSFET of claim 1, wherein the MOSFET is fabricated in a silicon-on-insulator technology.

132. The RF switch of claim 86, wherein the RF switch exhibits harmonic distortion, intermodulation distortion (IMD) and linearity performance characteristics under operation, and wherein the RF switch is capable of processing RF signals of a selected power level, and wherein the harmonic distortion, IMD, linearity characteristics, and power level processing of the RF switch are improved by removal or control of the accumulated charge from the body of the shunt transistor grouping.

133. The RF switch of claim 86, wherein the RF switch comprises a single-pole, multi-throw switch.

26. An accumulated charge control floating body MOSFET (ACC MOSFET) adapted to control charge accumulated in the body of the MOSFET when the MOSFET is operated in an accumulated charge regime, comprising:

a) a gate, drain, source, floating body, and a gate oxide layer positioned between the gate and the floating body, wherein the ACC MOSFET operates in the accumulated charge regime when the MOSFET is operated in an off-state (non-conducting state) and charge accumulates within the body in a region proximate and underneath the gate oxide layer; and

b) a first accumulated charge sink (ACS) positioned proximate a first distal end of the floating body, wherein the ACS is in electrical communication with the floating body, and wherein the ACS removes or otherwise controls the accumulated charge in the ACC MOSFET body.

27. The ACC MOSFET of claim 26, wherein the ACC MOSFET further comprises an electrical contact region positioned proximate to and in electrical communication with the first ACS, wherein the electrical contact region facilitates electrical coupling to the first ACS.

28. The ACC MOSFET of claim 27, wherein the ACC MOSFET comprises an ACC NMOSFET, and wherein the source and drain both comprise N+ doped regions, the floating body and the first ACS both comprise P−

doped regions, and the electrical contact region comprises a P+ doped region.

29. The ACC MOSFET of claim 27, wherein the ACC MOSFET comprises an ACC NMOSFET, and wherein the source and drain both comprise N+ doped regions, the floating body and the first ACS both comprise P−

doped regions, and the electrical contact region comprises an N+ doped region that acts as a diode connection to the first ACS thereby inhibiting positive current flow into the first ACS and into the floating body under selected bias voltage conditions.

30. The ACC MOSFET of claim 27, wherein the ACC MOSFET comprises an ACC PMOSFET, and wherein the source and drain both comprise P+ doped regions, the floating body and the ACS both comprise N−

doped regions, and the electrical contact region comprises an N+0 doped region.

31. The ACC MOSFET of claim 27, wherein the ACC MOSFET comprises an ACC PMOSFET, and wherein the source and drain both comprise P+ doped regions, the floating body and the ACS both comprise N−

doped regions, and the electrical contact region comprises an P+ doped region that acts as a diode connection to the ACS thereby inhibiting positive current flow into the ACS and into the floating body under selected bias voltage conditions.

32. The ACC MOSFET of claim 27, wherein the electrical contact region and the ACS are coextensive.

33. The ACC MOSFET of claim 28, wherein the floating body and the ACS comprise a combined P−

doped region that may be fabricated in a single ion-implementation manufacturing step.

34. The ACC MOSFET of claim 28, wherein the floating body and the ACS comprise separate P−

doped regions that are coupled together.

35. The ACC MOSFET of claim 27, wherein the MOSFET body includes a channel region including a gate modulated conductive channel between the source and the drain, and wherein the source, drain and channel have carriers of identical polarity when the ACC MOSFET is operated in an on-state (conducting state), and wherein the ACC MOSFET operates in the accumulated charge regime when the MOSFET is biased to operate in the off-state and when the accumulated charge has a polarity that is opposite to the polarity of the source, drain and channel carriers.

36. The ACC MOSFET of claim 35, wherein the ACC MOSFET comprises an NMOSFET device, and wherein the accumulated charge comprises holes having “

P”

polarity.

37. The ACC MOSFET of claim 35, wherein the MOSFET comprises a PMOSFET device, and wherein the accumulated charge comprises electrons having “

N”

polarity.

38. The ACC MOSFET of claim 35, wherein the ACC MOSFET has a depleted or partially depleted channel region.

39. The ACC MOSFET of claim 26, wherein the ACS has an impedance greater than approximately 10⁶ ohms.

40. The ACC MOSFET of claim 26, wherein the ACS has an impedance less than approximately 10⁶ ohms.

41. The ACC MOSFET of claim 26, wherein the ACS is positioned a selected distance away from the source and drain thereby reducing parasitic capacitance effects associated with the ACS.

42. The ACC MOSFET of claim 26, wherein the ACS is coupled to the body at the first distal end of the floating body thereby reducing parasitic capacitance effects associated with the coupling of the ACS to the floating body.

43. The ACC MOSFET of claim 26, wherein the floating body has a width exceeding approximately 10 μ

m.

44. The ACC MOSFET of claim 26, wherein the ACC MOSFET includes a gate terminal electrically coupled to the gate, a drain terminal electrically coupled to the drain, a source terminal electrically coupled to the source, and an ACS terminal electrically coupled to the ACS.

45. The ACC MOSFET of claim 44, wherein the gate, drain, source and ACS terminals are coupled to their respective regions via low resistance contact regions.

46. The ACC MOSFET of claim 44, wherein the ACC MOSFET is biased to operate in the accumulated charge regime by applying selected bias voltages to the source, drain and gate terminals, and wherein accumulated charge is removed or otherwise controlled by coupling the ACS terminal to an accumulated charge sinking mechanism.

47. The ACC MOSFET of claim 46, wherein the accumulated charge is removed or otherwise controlled by applying a selected bias voltage V_ACS to the ACS terminal when the ACC MOSFET operates in the accumulated charge regime.

48. The ACC MOSFET of claim 47, wherein the ACC MOSFET comprises a depletion mode NMOSFET device, and wherein V_ACS is selected to be equal to or more negative than the lesser of the source bias voltage and the drain bias voltage.

49. The ACC MOSFET of claim 27, wherein the electrical contact region is positioned a selected distance away from the source, drain and body, thereby reducing parasitic capacitance effects associated with the ACS.

50. The ACC MOSFET of claim 35, further including a contact region overlap region positioned proximate a distal edge of the gate over the channel region of the body and over the gate oxide layer, wherein the overlap region ensures that all of the gate oxide layer is completely covered with dopant material that is the same as dopant material used to form the electrical contact region.

51. The ACC MOSFET of claim 50, wherein the electrical contact region is positioned a selected distance away from the distal edge of the gate thereby reducing or eliminating a region of increased threshold voltage in the MOSFET associated with the proximity of the overlap region to the distal edge of the gate.

52. The ACC MOSFET of claim 26, wherein the ACC MOSFET comprises a “

T-gate”

configured ACC MOSFET, and wherein the floating body forms a supporting member of the “

T-gate”

configured MOSFET and the first ACS forms a supported member of the “

T-gate”

configured MOSFET, and wherein the first ACS is positioned along the first distal end of the floating body and is in contact with at least some portion of the floating body.

53. The ACC MOSFET of claim 52, wherein the ACC MOSFET further comprises an electrical contact region positioned proximate and in electrical communication with the ACS, wherein the electrical contact region facilitates electrical coupling to the ACS.

54. The ACC MOSFET of claim 53, wherein the ACS has an impedance greater than approximately 10⁶ ohms.

55. The ACC MOSFET of claim 53, wherein the ACS has an impedance less than approximately 10⁶ ohms.

56. The ACC MOSFET of claim 26, wherein the ACC MOSFET comprises an “

H-gate”

configured ACC MOSFET, wherein the H-gate configured MOSFET includes the first and a second ACS positioned proximate the first and a second distal end of the floating body, respectively, and wherein the first and second ACSs are positioned on opposite ends of the floating body, and wherein the first ACS has an associated and respective first electrical contact region positioned proximate thereto and in electrical communication therewith, and wherein the second ACS has an associated and respective second electrical contact region positioned proximate thereto and in electrical communication therewith, and wherein the first and second ACSs are in electrical communication with the floating body.

57. The ACC MOSFET of claim 56, wherein the ACC MOSFET has a width, and wherein the first and second ACSs extend approximately the entire width of the ACC MOSFET.

58. The ACC MOSFET of claim 57, wherein the first and second ACSs extend beyond the width of the ACC MOSFET.

59. The ACC MOSFET of claim 57, wherein the first and second ACSs do not extend to the width of the ACC MOSFET.

60. The ACC MOSFET of claim 56, wherein the first and second ACSs have identical impedances.

61. The ACC MOSFET of claim 60, wherein the impedances of the first and second ACSs differ from one another.

62. The ACC MOSFET of claim 56, wherein the first electrical contact region is positioned a first selected distance away from the floating body, and wherein the second electrical contact region is positioned a second selected distance away from the floating body.

63. The ACC MOSFET of claim 62, wherein the first and second selected distances are identical.

64. The ACC MOSFET of claim 62, wherein the first and second selected distances differ from one another.

65. The ACC MOSFET of claim 56, wherein the ACSs are approximately rectangular.

66. The ACC MOSFET of claim 56, wherein the ACSs are approximately circular.

67. The ACC MOSFET of claim 56, wherein the ACSs are approximately square.

68. A four-terminal accumulated charge control floating body MOSFET (ACC MOSFET) device, adapted to control charge accumulated in the body of the MOSFET when the MOSFET is operated in an accumulated charge regime, comprising:

a) a gate, drain, source, floating body, and a gate oxide layer positioned between the gate and the floating body, wherein the ACC MOSFET operates in the accumulated charge regime when the MOSFET is operated in an off-state (non-conducting state) and charge accumulates within the body in a region proximate and underneath the gate oxide layer;

b) an accumulated charge sink (ACS) positioned proximate a distal end of the floating body, wherein the ACS is in electrical communication with the floating body; and

c) a gate terminal electrically coupled to the gate, a drain terminal electrically coupled to the drain, a source terminal electrically coupled to the source, and an ACS terminal electrically coupled to the ACS;

wherein the charge accumulated in the body is controlled or removed from the body via the ACS terminal when the MOSFET operates in the accumulated charge regime.

69. The four-terminal ACC MOSFET of claim 68, wherein the gate and ACS terminals are electrically coupled together.

70. The four-terminal ACC MOSFET of claim 69, wherein the accumulated charge is removed from the body via the ACS and gate terminals when the ACC MOSFET device is biased to operate in the accumulated charge regime.

71. The four-terminal ACC MOSFET of claim 69, wherein a diode is coupled between the gate and ACS terminals such that the diode prevents positive current flow into the ACC MOSFET body when the MOSFET is operated in an on-state (conducting state) condition and the diode is reverse-biased.

72. The four-terminal ACC MOSFET of claim 71, wherein the diode has an associated voltage drop across the diode, and wherein the voltage drop across the diode may be selectively reduced by increasing a width of the diode.

73. The four-terminal ACC MOSFET of claim 68, wherein the ACS terminal is coupled to an accumulated charge sinking mechanism.

74. The four-terminal ACC MOSFET of claim 73, wherein the ACS accumulated charge sinking mechanism comprises a control circuit adapted to control or remove the accumulated charge from the body when the ACC MOSFET operates in the accumulated charge regime.

75. The four-terminal ACC MOSFET of claim 73, wherein the accumulated charge sinking mechanism produces a selectable accumulated charge sink bias voltage (V_ACS), and wherein the V_ACS is selected such that the accumulated charge is removed from the body when the ACC MOSFET operates in the accumulated charge regime.

76. The four-terminal ACC MOSFET of claim 75, wherein the accumulated charge sink bias voltage V_ACS is driven by a source having a relatively high impedance.

77. The four-terminal ACC MOSFET of claim 76, wherein the accumulated charge sink bias voltage V_ACS is driven by a source having an impedance greater than approximately 10⁶ ohms.

78. The four-terminal ACC MOSFET of claim 75, wherein the gate, drain and source have associated and respective gate (Vg), drain (Vd) and source (Vs) bias voltages, and wherein the ACS bias voltage V_ACS is selected to be equal to or more negative than the lesser of both Vs and Vd, thereby conveying the accumulated rhetorical charge from the body when the MOSFET operates in the accumulated charge regime.

79. The four-terminal ACC MOSFET of claim 68, wherein the gate and ACS terminals are electrically coupled together via a clamping circuit configured in series between the ACS and gate terminals.

80. The four-terminal ACC MOSFET of claim 79, wherein the clamping circuit limits the flow of current from the ACS terminal during the accumulated charge regime thereby ensuring that the accumulated charge is controlled or removed from the MOSFET body during the accumulated charge regime.

81. The four-terminal ACC MOSFET of claim 79, wherein the clamping circuit comprises a depletion-mode MOSFET configured in series between the ACS terminal and the gate terminal.

82. The four-terminal ACC MOSFET of claim 81, wherein the depletion-mode MOSFET has a selected saturation current, and wherein the saturation current limits the flow of current from the ACS terminal during the accumulated charge regime.

83. The four-terminal ACC MOSFET of claim 82, wherein the depletion-mode MOSFET enters saturation upon reaching a predefined threshold, and wherein the saturation current is selected by setting the threshold to a desired value.

84. The four-terminal ACC MOSFET of claim 81, wherein the clamping circuit further comprises a diode configured in series with the depletion-mode MOSFET.

85. The four-terminal ACC MOSFET of claim 71, further comprising an AC shorting capacitor coupled in parallel across the diode, wherein the AC shorting capacitor ensures that nonlinearity characteristics of the diode are not excited when AC signals present across the diode.

97. The RF switch of claim 85, wherein the switch transistor grouping comprises a plurality of MOSFETs arranged in a stacked configuration, and wherein the shunt transistor grouping comprises a plurality of ACC MOSFETs arranged in a stacked configuration.

116. A method of controlling the linearity characteristics of a floating body MOSFET, wherein the floating body MOSFET includes an accumulated charge sink (ACS) operatively coupled to the body of the MOSFET and adapted to remove or otherwise control accumulated charge that accumulates in the MOSFET body when the MOSFET is operated in a off-state (non-conducting state), comprising:

a) configuring the floating body MOSFET to operate in a selected circuit;

b) biasing the floating body MOSFET to operate in an accumulated charge regime; and

c) removing or otherwise controlling the accumulated charge.

117. The method of claim 116, wherein the step b) of biasing the MOSFET to operate in the accumulated charge regime comprises biasing the MOSFET into the off-state.