Semiconductor circuit arrangement and method

• US 20070018274A1
• Filed: 06/30/2006
• Published: 01/25/2007
• Est. Priority Date: 06/30/2005
• Status: Abandoned Application

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Meiser, Andreas, Bonart, Dietrich, Gruber, Hermann, Hartner, Walter
• Application Number:
  US11/478,912
• Publication Number:
  US 20070018274A1
• Time in Patent Office: Days
• US Class Current: 257/506
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 28/60 Electrodes

Abstract

One aspect of the present invention relates to a semiconductor circuit arrangement and to a method for producing the latter. One aspect of the invention is that, as a result of a connecting trench structure and an isolation trench structure of a semiconductor circuit being in direct spatial proximity with respect to one another, an additional capacitor device is formed. The capacitance of said capacitor device is connected as a usable capacitance for the semiconductor circuit and is connected to the latter.

Claims

1. A semiconductor circuit arrangement comprising:

a semiconductor circuit;

a connecting trench structure for the semiconductor circuit; and

an isolation trench structure for the semiconductor circuit;

wherein the connecting trench structure and the isolation trench structure are formed in spatial proximity with respect to one another such that an additional capacitor device for the semiconductor circuit is formed thereby; and

wherein the capacitance of said capacitor device is connected as a usable capacitance for the semiconductor circuit and is connected thereto.

2. The semiconductor circuit arrangement of claim 1, wherein the connecting trench structure and the isolation trench structure are formed at a comparatively small lateral distance from one another.

3. The semiconductor circuit arrangement of claim 1, wherein the connecting trench structure and the isolation trench structure are formed in a semiconductor material region or in an epitaxial region on a semiconductor material region with a mesa region in between.

4. The semiconductor circuit arrangement of claim 1, wherein the connecting trench structure for the semiconductor circuit is formed with a first electrically conductive material region, which is electrically contact-connected to the walls and to the bottom of the connecting trench structure, as a first electrode device of the additional capacitor device.

5. The semiconductor circuit arrangement of claim 1, wherein the isolation trench structure for the semiconductor circuit is formed with a second electrically conductive material region, which is electrically insulated from the walls and from the bottom of the isolation trench structure, as a second electrode device of the additional capacitor device.

6. The semiconductor circuit arrangement of claim 1, wherein the additional capacitor device and its capacitance are formed in such a manner that they are laterally delimited by an additional delimiting isolation trench structure (40) and are closed.

7. The semiconductor circuit arrangement of claim 6, wherein the additional delimiting isolation trench structure for the semiconductor circuit is formed with a third electrically conductive material region which is electrically insulated from the walls and from the bottom of the additional delimiting isolation trench structure.

8. The semiconductor circuit arrangement of claim 1, wherein the isolation trench structure is formed such that it laterally surrounds the connecting trench structure in a concentric manner.

9. The semiconductor circuit arrangement of claim 6, wherein the additional delimiting isolation trench structure is formed such that it laterally surrounds the connecting trench structure and the isolation trench structure in a concentric manner.

10. The semiconductor circuit arrangement of claim 6, wherein the connecting trench structure, the isolation trench structure and/or the additional delimiting isolation trench structure is/are filled and formed, as a respective first, second and third electrically conductive material region, with a filling of a material or a combination of materials from the group comprising polysilicon, metals and tungsten.

11. The semiconductor circuit arrangement of claim 1, wherein the semiconductor circuit is in the form of a power semiconductor circuit and in the form of a smart power circuit.

12. A method for producing a semiconductor circuit arrangement comprising:

forming a semiconductor circuit;

forming a connecting trench structure for the semiconductor circuit;

forming an isolation trench structure for the semiconductor circuit;

forming the connecting trench structure and the isolation trench structure in spatial proximity with respect to one another in such a manner that an additional capacitor device for the semiconductor circuit is formed thereby; and

connecting the capacitance of said capacitor device to the semiconductor circuit as a usable capacitance for the semiconductor circuit.

13. The method of claim 12, further comprising forming the connecting trench structure and the isolation trench structure at a comparatively small lateral distance from one another.

14. The method of claim 12, further comprising forming the connecting trench structure and the isolation trench structure in a semiconductor material region or in an epitaxial region on a semiconductor material region with a mesa region (M1) in between.

15. The method of claim 12, further comprising forming the connecting trench structure for the semiconductor circuit with a first electrically conductive material region, which is electrically contact-connected to the walls and to the bottom of the connecting trench structure, as a first electrode device of the additional capacitor device.

16. The method of claim 12, further comprising forming the isolation trench structure for the semiconductor circuit with a second electrically conductive material region, which is electrically insulated from the walls and from the bottom of the isolation trench structure, as a second electrode device of the additional capacitor device.

17. The method of claim 12, further comprising forming the additional capacitor device and its capacitance in such a manner that they are laterally delimited by an additional delimiting isolation trench structure and are closed.

18. The method of claim 17, further comprising forming the additional delimiting isolation trench structure for the semiconductor circuit with a third conductive material region which is electrically insulated from the walls and from the bottom of the additional delimiting isolation trench structure.

19. The method of claim 12, further comprising forming the isolation trench structure such that it laterally surrounds the connecting trench structure in a concentric manner.

20. The method of claim 17, further comprising forming the additional delimiting isolation trench structure such that it laterally surrounds the connecting trench structure and the isolation trench structure in a concentric manner.

21. The method of claim 17, further comprising filling and forming the connecting trench structure, the isolation trench structure and/or, the additional delimiting isolation trench structure as a respective first, second and third electrically conductive material region with a filling comprising a material or a combination of materials from the group comprising polysilicon, metals and tungsten.

22. The method of claim 12, further comprising forming the semiconductor circuit as a power semiconductor circuit and as a smart power circuit.

23. A semiconductor circuit arrangement comprising:

a semiconductor circuit;

a connecting trench structure for the semiconductor circuit;

an isolation trench structure for the semiconductor circuit; and

means forming an additional capacitor device coupled to the semiconductor circuit such that capacitance of the capacitor device is used by the semiconductor device.