Fabrication of inductors in transformer based tank circuitry

• US 20070018767A1
• Filed: 07/19/2005
• Published: 01/25/2007
• Est. Priority Date: 07/19/2005
• Status: Active Grant

• Current Assignee: Intellectual Ventures Holding 81 LLC (Intellectual Ventures LLC)
• Original Assignee: LC Tank LLC
• Inventors: Gabara, Thaddeus
• Granted Patent: US 7,786,836 B2
• Time in Patent Office: Days
• US Class Current: 336/200
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/0053 with means to reduce eddy currents
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2924/19015 including thin film passive components
• CPC Class Codes: H01L 2924/19042 being an inductor
• CPC Class Codes: H01L 2924/19104 on the semiconductor or solid-state device, i.e. passive-on-chip

Abstract

Placing inductors or resistors in parallel causes the combined value of inductance or resistance to decrease according to the parallel combination rule. This invention decreases the parasitic resistance of an inductor by placing several inductors in parallel. Furthermore, by careful placement of these inductors, the mutual inductance between these inductors can be used to increase the equivalent inductance value to a value near that of the original inductance value of a single inductor. Thus, it is possible to create an inductance with a much lower value of parasitic resistance. This invention allows the formation of high Q inductors and would be beneficial in any circuit design requiring inductances. Another aspect of this invention is that the coils can be partitioned to minimize eddy current losses. This invention can easily be implemented in a planar technology. Simulations of several tank circuits indicate that the power dissipation can be reduced 3 to 4 times when compared to conventional techniques.

Claims

1. A planar inductor comprising;

at least one integrated circuit substrate,

a first lead and a second lead,

an element comprising;

a metallic portion formed on a dielectric layer, and

the metallic portion having an input port and an output port,

at least two elements coupled together, whereby

the input ports are coupled to the first lead, and

the output ports are coupled to the second lead.

2. The inductor of claim 1 whereby;

the metallic portion is formed into a coil.

3. The inductor of claim 1 comprising;

a plurality of alternating metallization and dielectric layers, whereby

at least one element is positioned over another.

4. The inductor of claim 3 whereby;

the coupling means comprises;

at least one via.

5. The inductor of claim 3 whereby;

at least one of the metallization and dielectric layers are formed on a second substrate.

6. The inductor of claim 5 whereby;

the coupling means comprises;

at least one solder bump.

7. A planar inductor comprising;

at least one integrated circuit substrate,

a first lead and a second lead,

an element comprising;

a metallic portion formed on a dielectric layer, and

the metallic portion having an input port and an output port,

a compound comprising;

an input terminal and an output terminal,

at least two elements coupled in series, wherein

the input port of the first element is coupled to the input terminal, and

the output port of the last element is coupled to the output terminal,

at least two compounds coupled together, whereby

the input terminals are coupled to the first lead, and

the output terminals are coupled to the second lead.

8. The inductor of claim 7 whereby;

the metallic portion is formed into a coil.

9. The inductor of claim 7 comprising;

a plurality of alternating metallization and dielectric layers, whereby

at least one element is positioned over another.

10. The inductor of claim 9 whereby;

the coupling means comprises;

at least one via.

11. The inductor of claim 9 whereby;

at least one of the metallization and dielectric layers are formed on a second substrate.

12. The inductor of claim 11 whereby;

the coupling means comprises;

at least one solder bump.

13. A planar inductor comprising;

at least one integrated circuit substrate,

a plurality of alternating metallization and dielectric layers,

a first lead and a second lead,

an element comprising;

a first metallic portion formed on a first dielectric layer,

the first metallic portion having an input port and a first port,

a second metallic portion formed on a second dielectric layer,

the second metallic portion having a output port and an second port, and

at least one via connecting the first port to the second port,

at least two elements coupled together, whereby

the input ports are coupled to the first lead, and

the output ports are coupled to the second lead.

14. The inductor of claim 13 whereby;

the metallic portions form part of a coil.

15. The inductor of claim 13 whereby;

at least one element is positioned over another.

16. The inductor of claim 13 whereby;

the second metallic portion of one of the elements is positioned over the first metallic portion of another element.

17. The inductor of claim 16 whereby;

the coupling means comprises;

at least one via.

18. The inductor of claim 16 whereby;

at least one of the metallization and dielectric layers are formed on a second substrate.

19. The inductor of claim 18 whereby;

the coupling means comprises;

at least one solder bump.

20. A method for manufacturing an inductor in an integrated circuit, the method comprising the steps of;

depositing a metal layer onto a first dielectric layer,

patterning the metal layer to define a first port, a second port and a segment length that connects the first port to the second port, and further

patterning the segment to define at least one lengthwise openings in the metal layer, thereby manufacturing the inductor in the integrated circuit.

21. The method of claim 20, wherein the manufacturing of an inductor in an integrated circuit comprises;

patterning the segment length into a coil.

22. A method for manufacturing an inductor in an integrated circuit, the method comprising the steps of;

depositing a first metal layer onto a first dielectric layer,

patterning the first metal layer to define a first port, a second port and a segment length that connects the first port to the second port,

depositing at least one additional dielectric layer over the first metal layer,

defining via openings in the additional dielectric layers over the first port and the second port,

depositing a conductive material into the via openings,

depositing a second metal layer onto the additional dielectric layer,

patterning the second metal layer to define a third port, a fourth port and a second segment length that connects the third port to the fourth port, and further

positioning the third port over the first port and the fourth port over the second port and the second segment over the first segment, thereby

manufacturing the inductor in the integrated circuit.

23. The method of claim 22, wherein the manufacturing of an inductor in an integrated circuit comprises;

patterning the first segment length and the second length into a coil.