Multiple stage delta sigma modulators

• US 20070018871A1
• Filed: 09/29/2006
• Published: 01/25/2007
• Est. Priority Date: 04/02/2004
• Status: Active Grant

• Current Assignee: Kaben Wireless Silicon Inc.
• Original Assignee: Kaben Research Inc.
• Inventors: Riley, Tom
• Granted Patent: US 7,324,030 B2
• Time in Patent Office: Days
• US Class Current: 341/143
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider
• CPC Class Codes: H03M 7/3006 Compensating for, or preventing of, undesired influence of physical parameters
• CPC Class Codes: H03M 7/3022 having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type

Abstract

A delta sigma modulator which employs a plurality of accumulators with non-power-of-2 modulus. The accumulators may consist of a primary non-power-of-2 modulus accumulator and a secondary non-power-of-2 modulus accumulator. The number of bits in the primary accumulators affects the frequency resolution of the resultant delta sigma fractional N frequency synthesizer and can be the minimum number of bits required by the resolution specification. The secondary accumulator integrates the carry outputs of its corresponding primary accumulators. This integration results in attenuating the dc content of the modulator output by a factor equal to the modulus of the secondary accumulators and may require compensation in the recombination block.

Claims

1. A delta sigma modulator for use with a delta sigma frequency synthesizer, the modulator comprising:

a first group of accumulators;

a second group of accumulators;

a recombiner producing an output of said modulator; and

a bit stream generator,

wherein

each group of accumulators comprises a plurality of accumulators coupled to one another;

said second group of accumulators receives an input representing a fractional portion of divider division ratio used by said delta sigma frequency synthesizer;

said first group of accumulators receives input from said second group of accumulators;

at least one accumulator in said second group of accumulators receives an input from said bit stream generator;

said recombiner receives input from said first group of accumulators; and

both of said first and second groups of accumulators are synchronously clocked.

2. A modulator according to claim 1 wherein each accumulator in said first group of accumulators has a modulus selected from a group which excludes values 2ⁿ where n is a natural number.

3. A modulator according to claim 1 wherein each accumulator in said second group of accumulators has a modulus selected from a group which excludes values 2ⁿ where n is natural number.

4. A modulator according to claim 2 wherein each accumulator in said first group of accumulators has a modulus of 3.

5. A modulator according to claim 3 wherein each accumulator in said second group of accumulators has modulus equal to a ratio between a frequency available to said delta sigma frequency synthesizer and a frequency resolution desired from said synthesizer.

6. A modulator according to claim 5 wherein each accumulator in said second group of accumulators has a modulus of 65.

7. A modulator according to claim 1 wherein each accumulator in said first and second groups of accumulators comprises:

an adder receiving inputs to the accumulator;

a quantized receiving an output of said adder;

a multiple bit register receiving as result output of said quantized; and

a delay element receiving a carry output of said quantized,

and wherein

an output of said delay element is a carry output of said accumulator;

an output of said register is a result of said accumulator; and

said output of said register is also received by said adder.

8. A modulator according to claim 7 wherein said quantizer for each accumulator for said first group outputs a 1 when an output of said adder is greater than 2.

9. A modulator according to claim 7 wherein said quantized for each accumulator for said second group outputs a 1 when an output of said adder is greater than 65.

10. A modulator according to claim 1 wherein said bit stream generator is an accumulator having a constant as an input value.

17. A modulator according to claim 1 wherein said recombiner implements a filter having a transfer function of:

Y=(C1d3(1+Z<sup>−

1</sup>+Z<sup>−

2</sup>)+(C2d2+(C3d1+C4(1Z<sup>−

1</sup>))(1−

Z<sup>−

1</sup>))(1−

Z<sup>−

3</sup>)

where

Y is an output of said modulator;

C1, C2, C3, C4 are inputs to said recombiner and are each received from accumulators from said first group and

C1d3=C1Z<sup>−

3</sup>

C2d2=C2X<sup>−

2</sup>

C3d1=C3Z<sup>−

1</sup>.

11. A delta sigma modulator for use in a delta sigma frequency synthesizer, the delta sigma modulator comprising:

a first group of cascaded accumulators, said first group of accumulators including at least one accumulator having a modulus selected from a group of values which excludes 2ⁿ, n being a natural number, at least one of said first group of accumulators receiving an input from another of said first group of accumulators;

a second group of cascaded accumulators, at least one of said second group of accumulators receiving an input from another of said second group of accumulators;

a recombiner producing an output of said modulator; and

a bit stream generator,

wherein

at least one of said first group of accumulators receives an input from one of said second group of accumulators;

each one of said second group of accumulators has a modulus equal to a ratio between a frequency input to said synthesizer and a desired frequency resolution;

each one of said accumulators in said first group produces an output received by said recombiner; and

at least one of said accumulators in said second group of accumulators receives an output of said generator.

12. A modulator according to claim 11 wherein each accumulator in said second group of accumulators has a modulus selected from a group which excludes values 2ⁿ where n is natural number.

13. A modulator according to claim 11 wherein each accumulator in said first and second groups of accumulators comprises:

an adder receiving inputs to the accumulator;

a quantized receiving an output of said adder;

a multiple bit register receiving as result output of said quantized; and

a delay element receiving a carry output of said quantized, and wherein

an output of said delay element is a carry output of said accumulator;

an output of said register is a result of said accumulator; and

said output of said register is also received by said adder.

14. A modulator according to claim 11 wherein said recombiner includes a filter having a DC gain equal to a multiple of the modulus of said at least one accumulator in said first group of accumulators.

15. A modulator according to claim 11 wherein said output of said generator acts as a dithering signal for at least one of said accumulators in said second group of accumulators.

16. A modulator according to claim 11 wherein said recombiner implements a filter having a transfer function of:

Y=(C1d3(1+Z<sup>−

1</sup>+Z<sup>−

2</sup>)+(C2d2+(C3d1+C4(1−

Z<sup>−

1</sup>))(1−

Z<sup>−

1</sup>))(1−

Z³)

where

Y is an output of said modulator;

C1, C2, C3, C4 are inputs to said recombiner and are each received from accumulators from said first group and

C1d3=C1Z<sup>−

3</sup>

C2d2=C2X<sup>−

2</sup>

C3d1=C3Z<sup>−

1</sup>.