Semiconductor memories with block-dedicated programmable latency register

• US 20070019481A1
• Filed: 04/20/2006
• Published: 01/25/2007
• Est. Priority Date: 07/19/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Chul
• Granted Patent: US 7,486,575 B2
• Time in Patent Office: Days
• US Class Current: 365/193
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

An apparatus and method to delay output of data from different regions of a memory device in response to a read enable signal, the delaying of the output of data is based on the location of the regions of the memory device with respect to an output circuit that receives the data, wherein the different regions of the memory device have different CAS latency values dedicated to each region to set the delay time of each region of the memory device.

Claims

1. A semiconductor memory device, comprising:

at least one memory bank having a plurality of memory blocks to store data, the data stored in the memory blocks capable of being read in response to a read command;

a control unit to generate a plurality of CL values and to dedicate the CL values to predetermined ones of the memory blocks to be read; and

an output circuit to output the data in response to a read signal activated by the read command, wherein the output circuit outputs the data from each of the memory blocks based on the dedicated CL values.

2. The semiconductor memory device of claim 1, wherein the control unit comprises:

a CL register including a plurality of sets of mode registers, each of the sets of mode registers to generate the plurality of CL values; and

a CL Mux unit to select one of the plurality of CL values from each set of mode registers responsive to a column address within the read command and to dedicate the selected CL values to the predetermined ones of the memory blocks based on predetermined conditions of the memory blocks.

3. The semiconductor memory device of claim 2, wherein the predetermined conditions of the memory blocks includes a location of the memory blocks with respect to the output circuit in which the data is outputted.

4. A latency control unit usable with a memory device having a plurality of memory blocks to store data, comprising:

a CL register including at least one set of mode registers, each set of mode registers to generate one or more CAS latency values and being dedicated to one of the memory blocks;

a CL Mux to receive the generated CAS latency values from the at least one set of mode registers and to select one of the received CAS latency values based on a signal containing information on the memory blocks to be read; and

an output enable circuit to receive the selected CAS latency value and a read enable signal activated by a read command and to output an output enable signal to an output circuit.

5. The latency control unit of claim 4, wherein the output circuit outputs the data stored in accessed memory blocks according to the read command based on the selected CAS latency value and the output enable signal.

6. A latency control unit usable with a memory device having a plurality of memory blocks to store data and a data output circuit to enable output of the stored data from the memory blocks in accordance with a read enable signal, the latency control unit comprising:

a latency determining unit to determine a plurality of latency values, and to select predetermined ones of the latency values based on an address signal indicating locations of the memory blocks to be read; and

an output enable unit to receive the latency values output from the latency determining unit and to apply the latency values to the data output circuit to delay output of data from the plurality of memory blocks, wherein the data is output according to predetermined ones of the plurality of latency values based on the location of the memory block in which the data is being output.

7. A memory device comprising:

at least one memory bank including a plurality of memory blocks;

an address buffer to receive an address signal, to output MRS addresses to set a CL mode when an MRS command is input, and to output addresses of the address signal when a read command is input;

an address decoder to decode the addresses and select one of the memory blocks having block addresses;

a command decoder to receive the MRS command and output a pMRS signal, and to receive the read command and to output a read enable signal; and

a CAS latency control unit to receive the MRS addresses and the pMRS signal when the MRS command is input so that the CL mode having a plurality of CL values is set, to receive the block addresses to activate one of the plurality of CL values and the read enable signal, and to output an output enable signal to an output circuit according to the activated CL value, wherein the output circuit outputs read data from the selected memory block responsive to the output enable signal.

8. The memory device of claim 7, wherein the CAS latency control unit comprises:

a CL register including a plurality of mode registers each generating predetermined CL values based on the MRS addresses when the pMRS signal is activated;

a CL Mux unit to activate one of the CL values from each of the mode registers according to the block addresses; and

an output enable circuit to receive the read enable signal and the activated CL value, to delay the read enable signal by a number of clocks indicating the activated CL value, and to output the delayed read enable signal as the output enable signal.

9. A memory device comprising:

an output circuit;

a plurality of memory blocks that are different distances from the output circuit; and

a CAS latency control part to operate the output circuit in a plurality of modes including at least a first mode in which the output circuit is operated with a CAS latency value that is the same for accessing the plurality of memory blocks and a second mode in which the output circuit is operated with CAS latency values that are different for accessing the plurality of memory blocks.

10. The memory device of claim 9, wherein the memory device comprises a synchronous dynamic random access memory having an outer DQ inner clock (ODIC) architecture.

11. The memory device of claim 9, wherein the plurality of blocks comprise a plurality of memory banks.

12. The memory device of claim 11, wherein the plurality of blocks further comprise a plurality of regions within the plurality of memory banks.

13. The memory device of claim 9, wherein the CAS latency control part is programmable between the plurality of modes using two or more bits of a mode register set (MRS) command.

14. The memory device of claim 9, wherein the CAS latency control part receives a memory address of one of the plurality of memory blocks to be accessed from a read command, and selects among the different CAS latency values according to the received memory address when the output circuit is operated in the second mode.

15. The memory device of claim 9, wherein the CAS latency control part comprises:

a plurality of registers corresponding to the plurality of memory blocks to store the respective CAS latency values; and

a multiplexer to select from among the plurality of respective CAS latency values according to whether the CAS latency control part operates in the first mode or the second mode.

16. The memory device of claim 15, wherein the multiplexer receives an address of a current memory block being accessed and selects a CAS latency value according to the received address.

17. The memory device of claim 16, wherein the CAS latency control part further comprises:

an output enable circuit to receive the selected CAS latency value and a read enable signal associated with a read command and to delay the read enable signal by a number of clock cycles that corresponds to the selected CAS latency value and to apply an output enable signal that corresponds to the delayed read enable signal to the output circuit.

18. The memory device of claim 16, wherein the received address comprises at least one of a bank address, a column address, and a row address.

19. The memory device of claim 16, wherein the plurality of memory blocks comprise:

four memory banks disposed in each corner of a memory chip on which the memory device is implemented such that the output circuit is disposed on one side of the memory chip in between two memory banks; and

four memory regions arranged among the four memory banks such that each of the four memory regions is a different distance from the output circuit.

20. The memory device of claim 19, wherein each of the memory regions extends over more than one of the memory banks.

21. The memory device of claim 20, wherein first ones of the memory regions extend along a row direction of the memory banks, and second ones of the memory regions extend along a column direction of the memory banks.

22. The memory device of claim 15, wherein:

the plurality of registers comprise a plurality of mode registers that are programmable by a series of bits of an MRS command received along an address bus; and

the multiplexer comprises a plurality of logic units to output a logic high value on an output that corresponds to the selected CAS latency value.

23. The memory device of claim 15, wherein the plurality of registers store the plurality of CAS latency values that corresponds to the plurality of memory blocks.

24. The memory device of claim 9, wherein the plurality of different CAS latency values correspond to different data access times of the plurality of memory blocks.

25. A memory device comprising:

a plurality of memory units; and

a control part to receive a current address associated with a read command, to select a CAS latency value on the fly from among a plurality of CAS latency values associated with the plurality of memory units according to the current address, and to apply the selected CAS latency value to an output circuit of the memory device.

26. The memory device of claim 25, wherein the plurality of memory units comprises:

a far memory unit having a long data access time and a corresponding CAS latency value; and

one or more near memory units having shorter access times and CAS latency values that are programmable to be less than or equal to the CAS latency value of the far memory unit.

27. A method of accessing data from a semiconductor memory device including a plurality of memory blocks, the method comprising:

setting a CL mode having a plurality of CL values to correspond to the plurality of memory blocks when an MRS command is input;

receiving an address to indicate which block is read when a read command is input;

selecting one of the plurality of CL values indicated by the received address;

delaying a read enable signal associated with the read command by a number of clocks designated by the selected CL value and outputting an output enable signal to an output circuit according to the delayed read enable signal; and

outputting data read from the block indicated by the address based on the output enable signal.

28. A method of accessing data from a semiconductor memory device including a plurality of memory banks each having a plurality of memory blocks therein to store data, the method comprising:

dedicating a plurality of CL values to be used by an output circuit that enables data stored in the plurality of memory blocks to be output according to the corresponding plurality of CL values;

receiving an address of a selected memory block to be read associated with a read command;

providing an enable signal that is delayed according to the CL value of the addressed memory block to the output circuit; and

outputting the data read from the addressed memory block according to when the delayed enable signal is received.

29. The method of claim 28, wherein the dedicating of the plurality of CL values to be used by an output circuit comprises dedicating different CL values to memory blocks having different distances from the output circuit.

30. The method of claim 28, wherein the CL values are dedicated to predetermined addresses of the memory blocks such that smaller CL values are applied to memory blocks which are closer to the output circuit and increasingly larger CL values are applied to memory blocks which are positioned increasingly farther away from the output circuit, such that a delay in outputting the data stored in the addressed memory blocks proportionally increases as a distance of the memory block from the output circuit increases.

31. A method of reading data from a memory device having a at least two memory blocks, comprising:

providing an address signal containing information pointing to at least two addresses of the memory device to be read;

selecting at least two CL values that delay for predetermined periods of time outputting of the data to be read from the memory device based on the address signal information; and

enabling output of the data to be read from the at least two addresses of the memory device at different delayed periods of time based on the CL value selected for the corresponding address upon receiving a read enable signal instructing the data to be read from the at least two addresses of the memory device.

32. The method of claim 31, wherein the address signal information includes information about the locations of the addresses of the memory blocks to be read.

33. A method of reading data from a memory device having a I/O pad and a plurality of memory blocks that are different distances from the I/O pad, the method comprising:

applying different CAS latency values to the plurality of memory blocks on the fly when a read command is input.

34. A method of managing data read commands in a memory device, the method comprising:

selecting different column address strobe (CAS) latency values to correspond to memory blocks having different data access times; and

delaying a read enable signal associated with each of the memory blocks according to the different CAS latency values when the different memory blocks are accessed.

35. The method of claim 34, wherein the selecting of the different CAS latency values comprises enabling a CAS latency mode having the different CAS latency values for each memory block to be set by an MRS command.

36. The method of claim 34, wherein the delaying of the read enable signal comprises:

receiving a read command having an address to read a specified memory block; and

selecting the CAS latency value that corresponds to the specified memory block according to the received address.

37. The method of claim 34, wherein the delaying of the read enable signal comprises:

delaying the read enable associated with a specified memory block by a number of clock cycles of the corresponding CAS latency value; and

providing an output enable signal to enable an output circuit having read data from the specified memory block according to the delayed read enable signal associated therewith.

38. The method of claim 34, wherein the selecting of the different CAS latency values comprises selecting a first CAS latency value for a near memory block and selecting a second CAS latency value for a far memory block through an MRS command, and the far memory block is the farthest memory block from an output circuit and the near memory block is closer to the output circuit than the far memory block.

39. The method of claim 38, wherein the selecting of the first CAS latency value comprises:

setting the first CAS latency value to be less than the second CAS latency value in a first mode of operation; and

setting the first CAS latency value to be equal to the second CAS latency value in a second mode of operation.