Data clock recovery system and method employing phase shifting related to lag or lead time

• US 20070019773A1
• Filed: 07/21/2005
• Published: 01/25/2007
• Est. Priority Date: 07/21/2005
• Status: Abandoned Application

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Zhou, Dacheng (Henry)
• Application Number:
  US11/186,515
• Publication Number:
  US 20070019773A1
• Time in Patent Office: Days
• US Class Current: 375/373
• CPC Class Codes: H03D 7/125 with field effect transistors

Abstract

A data clock recovery system is provided. A phase detector is configured to produce a first signal indicating whether a data clock lags or leads a preferred phase of the data clock in relation to an input data stream. A phase controller is configured to process the first signal to shift a phase of the data clock toward the preferred phase at a rate positively related to a length of time the data clock lags or leads the preferred phase.

Claims

1. A data clock recovery system, comprising:

a phase detector configured to produce a first signal indicating whether a data clock lags or leads a preferred phase in relation to an input data stream; and

a phase controller configured to process the first signal to shift a phase of the data clock toward the preferred phase at a rate positively related to a length of time the data clock lags or leads the preferred phase.

2. The system of claim 1, the phase controller comprising:

a first counter configured to generate a first count from the first signal;

a threshold comparator configured to activate a second signal when the first count exceeds a threshold;

a second counter configured to generate a second count from the second signal;

a frequency synthesizer configured to generate a third signal comprising a frequency that is positively related with an absolute value of the second count; and

a phase interpolator configured to generate the data clock, wherein the phase of the data clock is shifted according to the third signal.

3. The system of claim 1, the phase controller comprising:

a first counter configured to generate a first count from the first signal;

a threshold comparator configured to activate a second signal when the first count exceeds a threshold;

a second counter configured to generate a second count from the second signal;

a frequency synthesizer configured to generate a third signal comprising a frequency that is positively related with an absolute value of the second count;

a pulse generator configured to generate a pulse update signal comprising a pulse for each pulse of the second signal and the third signal; and

a phase interpolator configured to generate the data clock, wherein the phase of the data clock is shifted according to the phase update signal.

4. The system of claim 3, wherein the frequency of the third signal is proportional to the absolute value of the second count.

5. The system of claim 3, wherein the frequency synthesizer and the phase interpolator are configured to be driven by a local clock.

6. The system of claim 5, wherein the local clock comprises a multiphase local clock.

7. The system of claim 1, wherein the preferred phase of the data clock comprises a midpoint between logical transitions of the input data stream.

8. The system of claim 1, wherein the phase detector produces the first signal by way of sampling the input data stream with a plurality of phases of the data clock.

9. The system of claim 3, wherein the second signal comprises a pulse when the first count exceeds the threshold.

10. The system of claim 1, wherein the input data stream comprises a serial input data stream.

11. The system of claim 1, wherein the input data stream comprises a parallel input data stream.

12. The system of claim 1, wherein the system is implemented by way of one of an application-specific integrated circuit, a digital signal processor, a microprocessor, and a microcontroller.

13. A data communication system comprising the system of claim 1.

14. A method for recovering data clock information from a communication signal, the method comprising:

generating a first signal indicating whether a data clock lags or leads a preferred phase in relation to an input data stream;

advancing a phase of the data clock at a rate positively related to a first length of time the first signal indicates the data clock lags the preferred phase; and

delaying the phase of the data clock at a rate positively related to a second length of time the first signal indicates the data clock leads the preferred phase.

15. The method of claim 14, wherein advancing and delaying the phase of the data clock comprises:

counting transitions of the first signal to yield a first count;

comparing the first count with a threshold;

activating a second signal while the first count exceeds the threshold;

counting transitions of the second signal to generate a second count;

generating a third signal comprising a frequency that is positively related with the absolute value of the second count; and

generating the data clock, wherein the phase of the data clock is shifted at a rate indicated by the frequency of the third signal.

16. The method of claim 15, wherein the frequency of the third signal is proportional to the absolute value of the second count.

17. The method of claim 15, wherein the phase of the data clock is also shifted according to the second signal.

18. The method of claim 15, further comprising generating a local clock from which the data clock is generated.

19. The method of claim 18, wherein the local clock comprises a multiphase local clock.

20. The method of claim 14, wherein the preferred phase comprises a midpoint between transitions of the input data stream.

21. The method of claim 14, wherein generating the first signal comprises comparing the phase of the input data stream with a plurality of phases of the data clock.

22. The method of claim 15, wherein the second signal comprises a pulse when the first count exceeds the threshold.

23. The method of claim 14, wherein the input data stream comprises a serial input data stream.

24. The method of claim 14, wherein the input data stream comprises a parallel input data stream.

25. The method of claim 14, wherein the method is executed by way of one of an application-specific integrated circuit, a digital signal processor, a microprocessor, and a microcontroller.

26. A data communication system comprising the method of claim 14.

27. A data clock recovery system, comprising:

means for generating a first signal indicating whether a data clock lags or leads a preferred phase in relation to an input data stream; and

means for shifting a phase of the data clock toward the preferred phase at a rate that is positively related to a length of time the first signal indicates the data clock leads or lags the preferred phase.

28. The system of claim 27, wherein means for shifting the phase of the data clock comprises:

means for generating a first count based on the first signal;

means for comparing the first count with a threshold;

means for counting each time the first count exceeds the threshold;

means for generating a third signal comprising a frequency that is positively related with the absolute value of the second count; and

means for generating the data clock, wherein the phase of the data clock is shifted at a rate corresponding to the frequency of the third signal.

29. The system of claim 28, wherein the frequency of the third signal is proportional to the absolute value of the second count.

30. The system of claim 28, further comprising means for generating a local clock from which the data clock is generated.

31. The system of claim 30, wherein the local clock comprises a multiphase local clock.

32. The system of claim 27, wherein the preferred phase comprises a midpoint between transitions of the input data stream.

33. The system of claim 27, wherein means for generating the first signal comprises means for comparing a phase of the input data stream with a plurality of phases of the data clock.

34. The system of claim 27, wherein the input data stream comprises a serial input data stream.

35. The system of claim 27, wherein the input data stream comprises a parallel input data stream.

36. The system of claim 27, wherein the system is implemented by way of one of an application-specific integrated circuit, a digital signal processor, a microprocessor, and a microcontroller.

37. A data communication system comprising the system of claim 27.