Method of manufacturing

• US 20070020668A1
• Filed: 07/06/2006
• Published: 01/25/2007
• Est. Priority Date: 02/06/1998
• Status: Abandoned Application

• Current Assignee: Affymetrix, Inc. (Thermo Fisher Scientific Incorporated)
• Original Assignee: Affymetrix, Inc. (Thermo Fisher Scientific Incorporated)
• Inventors: Goldberg, Martin, Rava, Richard
• Application Number:
  US11/483,346
• Publication Number:
  US 20070020668A1
• Time in Patent Office: Days
• US Class Current: 435/6
• CPC Class Codes: B01J 19/0046 Sequential or parallel reactions, e.g. for the synthesis of polypeptides or polynucleotides; Apparatus and devices for combinatorial chemistry or for making molecular arrays synthesis methods per se C40B50/00
• CPC Class Codes: B01J 2219/00378 Piezoelectric or ink jet dispensers
• CPC Class Codes: B01J 2219/00387 Applications using probes
• CPC Class Codes: B01J 2219/00432 Photolithographic masks
• CPC Class Codes: B01J 2219/00527 Sheets
• CPC Class Codes: B01J 2219/00529 DNA chips
• CPC Class Codes: B01J 2219/00536 in the shape of disks
• CPC Class Codes: B01J 2219/00585 Parallel processes
• CPC Class Codes: B01J 2219/0059 Sequential processes
• CPC Class Codes: B01J 2219/00596 Solid-phase processes
• CPC Class Codes: B01J 2219/00608 DNA chips
• CPC Class Codes: B01J 2219/0061 The surface being organic
• CPC Class Codes: B01J 2219/00612 the surface being inorganic
• CPC Class Codes: B01J 2219/00617 by chemical means
• CPC Class Codes: B01J 2219/00626 Covalent
• CPC Class Codes: B01J 2219/00644 the porous medium being present in discrete locations, e.g. gel pads
• CPC Class Codes: B01J 2219/00659 Two-dimensional arrays
• CPC Class Codes: B01J 2219/00662 Two-dimensional arrays within two-dimensional arrays
• CPC Class Codes: B01J 2219/00675 In-situ synthesis on the substrate
• CPC Class Codes: B01J 2219/00677 Ex-situ synthesis followed by deposition on the substrate
• CPC Class Codes: B01J 2219/00686 : Automatic
• CPC Class Codes: B01J 2219/00689 : using computers
• CPC Class Codes: B01J 2219/00693 : Means for quality control
• CPC Class Codes: B01J 2219/00695 : Synthesis control routines, e.g. using computer programs
• CPC Class Codes: B01J 2219/00711 : Light-directed synthesis
• CPC Class Codes: B01J 2219/00722 : Nucleotides
• CPC Class Codes: B01J 2219/00725 : Peptides
• CPC Class Codes: B82Y 30/00 : Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: C07K 1/045 : using devices to improve synthesis, e.g. reactors, special vessels
• CPC Class Codes: C07K 1/047 : Simultaneous synthesis of different peptide species; Peptide libraries
• CPC Class Codes: C40B 40/06 : Libraries containing nucleotides or polynucleotides, or derivatives thereof
• CPC Class Codes: C40B 50/14 : Solid phase synthesis, i.e. wherein one or more library building blocks are bound to a solid support during library creation; Particular methods of cleavage from the solid support
• CPC Class Codes: C40B 60/14 : for creating libraries
• CPC Class Codes: G07C 3/14 : Quality control systems

Abstract

A method of manufacturing items in parallel. Selected samples of items to be manufactured are subjected to additional steps in a manufacturing process. If such sample items meet the requisite quality control standard, remaining items are subjected to further manufacturing steps. If the sample items which have been further processed do not meet the requisite quality control standard, the lot from which the samples do not undergo the additional manufacturing step. Invention provides an improved method of manufacturing in that it prevents unnecessary manufacturing steps.

Claims

1. A method for manufacturing a plurality of items, said items comprising more than one sub-item, in serial, said method comprising;

manufacturing a plurality of items each item compirising more than one sub-item in serial over a period of time;

selecting a sample of manufactured items from the serial production process;

isolating said sub-item from said sample of manufactured items.

identifying a quality of the selected sub-item ; and

if said quality is determined to be satisfactory, then subjecting a remainder of said manufactured items produced in serial to further processing.

2. A method according to claim 1 wherein the plurality of the items to be manufactured in serial are wafers composed of more than one chips.

3. A method according to claim 2 wherein said wafers have from 400 to 6400 arrays.

4. A method according to claim 3 wherein the chips are comprised of biological material.

5. A method according to claim 4 wherein the biological material is selected from the group consisting of DNA, RNA, amino acids or analogs thereof.

6. A method according to claim 2 wherein said further processing is cutting the wafers into chips.

7. A method of manufacturing wafers comprising a plurality of arrays of nucleic acids, said method comprising

fabricating in serial a plurality of duplicate wafers, said wafers comprising nucleic acid arrays;

selecting at random at least one of said wafers;

isolating one or more of said nucleic acid arrays from said wafers;

performing a test on at least one of said arrays which identifies a particular quality of the array; and

if said array passes said testing step by meeting the quality, further processing a remainder of said of wafers.

8. The method of claim 7 wherein said wafers are manufactured by light directed synthesis.

9. The method of claim 7 wherein said wafers are manufacture by nucleic acid spotting.

10. The method of claim 7 wherein said step of further processing a remainder of wafers, comprising cutting said wafers into chips and inserting said chips into cartridges.

11. The method of claim 7 wherein said wafers are made by inkjet synthesis.

12. The method of claim 7 further comprising:

performing a second test which identifies a second property of said chip on at least one of said plurality of chips other than said first chips tested, and

if said at least one of said chips fails said second test, discarding said wafers.

13. The method of claim 12 further comprising:

performing a third test which identifies a third property of said chip on at least one of said plurality of chips other than said first and second chips tested, and

if said at least one of said chips fails said third test, discarding said wafers.