Image sensor having multi-gate insulating layers and fabrication method

• US 20070020796A1
• Filed: 05/22/2006
• Published: 01/25/2007
• Est. Priority Date: 07/19/2005
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Young-Hoon
• Application Number:
  US11/437,682
• Publication Number:
  US 20070020796A1
• Time in Patent Office: Days
• US Class Current: 438/57
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

An image sensor and related method of fabrication are disclosed. The image sensor includes a first gate insulating layer of first material layer type disposed in a sensor region of a semiconductor substrate, a second gate insulating layer of second material layer type disposed in an analog region of the semiconductor substrate, and a third gate insulating layer of third material layer type disposed in a digital region of the semiconductor substrate, wherein the first, second, and third material layer types are disparate in nature.

Claims

1. An image sensor comprising:

a first gate insulating layer of first material layer type disposed in a sensor region of a semiconductor substrate;

a second gate insulating layer of second material layer type disposed in an analog region of the semiconductor substrate; and

a third gate insulating layer of third material layer type disposed in a digital region of the semiconductor substrate;

wherein the first, second, and third material layer types are disparate.

2. The image sensor according to claim 1, wherein the first material layer type is silicon oxide.

3. The image sensor according to claim 2, wherein the second material layer type is a combination of silicon oxide and silicon oxynitride, and the third material layer type is silicon oxynitride.

4. The image sensor according to claim 1, wherein the sensor region comprises photodiodes.

5. The image sensor according to claim 1, wherein the digital region comprises a timing generator, a row decoder, a row driver, a latch unit, a column decoder and an image signal processor.

6. The image sensor according to claim 1, wherein the analog region comprises a correlated double sampler (CDS) and an analog to digital converter (ADC).

7. The image sensor according to claim 1, wherein the third material layer type is thinner than the first and second material layer types.

8. The image sensor according to claim 7, wherein the second material layer type is thicker than the first material layer type.

9. The image sensor according to claim 7, wherein a thickness for the second material layer type ranges between about two to four times a thickness for the third material layer type.

10. The image sensor according to claim 7, wherein the first material layer type comprises a nitrogen-free silicon oxide layer.

11. The image sensor according to claim 10, wherein the second material layer type is a combination of silicon oxide layer and silicon oxynitride, and the third material layer type is silicon oxynitride.

12. A method of fabricating an image sensor, comprising:

forming a first gate insulating layer on a substrate;

forming a first gate conductive layer pattern on the first gate insulating layer in a sensor region of the substrate;

selectively removing the first gate insulating layer from a digital region of the substrate;

forming an additional gate insulating layer on the substrate where the first gate insulating layer has been selectively removed from the digital region of the substrate, wherein the first gate insulating layer and the additional gate insulating layer in an analog region of the substrate form a second gate insulating layer, and the additional gate insulating layer in the digital region of the substrate form a third gate insulating layer; and

forming a second gate conductive layer pattern to cover the additional gate insulating layer in the analog and digital regions.

13. The method according to claim 12, wherein the first gate insulating layer is formed of a silicon oxide layer.

14. The method according to claim 13, wherein the additional gate insulating layer is formed of a silicon oxynitride layer.

15. The method according to claim 14, wherein the silicon oxynitride layer is formed using a thermal treatment process that employs a gas containing nitrogen atoms and oxygen atoms.

16. The method according to claim 14, wherein the silicon oxynitride layer is formed using a nitrogen plasma treatment process.

17. The method according to claim 12, further comprising patterning the first gate conductive layer pattern and the second gate conductive layer pattern to form first through third gate patterns in the sensor region, the analog region and the digital region respectively.

18. The method according to claim 17, further comprising forming a photodiode in the semiconductor substrate of the sensor region adjacent to one sidewall of the first gate pattern.

19. The method according to claim 18, further comprising forming spacers on sidewalls of the gate patterns.

20. The method according to claim 19, wherein forming the spacers comprises:

forming a spacer layer on the substrate having the photodiode; and

anisotropically etching the spacer layer.

21. The method according to claim 19, wherein forming the spacers comprises:

forming a spacer layer on the substrate having the photodiode;

forming a mask pattern on the spacer layer to cover the photodiode; and

anisotropically etching the spacer layer using the mask pattern as an etch mask, wherein a blocking layer composed of a portion of the spacer layer remains under the mask pattern while the spacer layer is anisotropically etched.

22. The method according to claim 21, further comprising implanting impurity ions into the semiconductor substrate using the gate patterns, the blocking layer and the spacers as ion implantation masks to form source/drain regions.