IMPROVED CMOS (Complementary Metal Oxide Semiconductor) TECHNOLOGY

• US 20070020830A1
• Filed: 07/21/2005
• Published: 01/25/2007
• Est. Priority Date: 07/21/2005
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Speranza, Anthony
• Granted Patent: US 7,271,044 B2
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts

Abstract

A method for forming semiconductor transistor. The method comprises providing a structure including (a) a semiconductor region, and (b) first and second dopant source regions on and in direct physical contact with the semiconductor region, wherein each region of the first and second dopant source regions comprises a dielectric material which contains dopants; causing the dopants to diffuse from the first and second dopant source regions into the semiconductor region so as to form first and second source/drain extension regions, respectively, wherein the first and second source/drain extension regions define a channel region disposed between; forming a gate dielectric region on a channel region; and forming a gate region on the gate dielectric region, wherein the gate dielectric region electrically insulates the gate region from the channel region.

Claims

1. A structure formation method, comprising:

providing a structure including;

(a) a semiconductor region comprising a semiconductor region top surface, and

(b) first and second dopant source regions on and in direct physical contact with the semiconductor region top surface, wherein each region of the first and second dopant source regions comprises a first dielectric material which contains first dopants;

causing the first dopants to diffuse from the first and second dopant source regions into the semiconductor region so as to form first and second source/drain extension regions, respectively, in the semiconductor region,

wherein the first and second source/drain extension regions define a channel region in the semiconductor region, and

wherein the channel region is (i) disposed between and in direct physical contact with the first and second source/drain extension regions and (ii) in direct physical contact with the semiconductor region top surface;

forming a gate dielectric region on the channel region after said causing the first dopants to diffuse is performed; and

forming a gate region on the gate dielectric region, wherein the gate dielectric region electrically insulates the gate region from the channel region.

2. The method of claim 1, wherein the first dielectric material comprises boron silicate glass.

3. The method of claim 1, wherein the first dielectric material comprises phosphorous silicate glass.

4. The method of claim 1, further comprising forming a standard transistor on a wafer, wherein the structure is on the wafer, and wherein said forming the standard transistor comprises (a) forming a gate stack on the wafer, wherein the gate stack comprises (i) a gate dielectric layer and (ii) a gate electrode region, wherein the gate dielectric layer is sandwiched between and electrically insulates a channel portion in the wafer and the gate electrode region, then (b) forming first and second source/drain portions (i) in the wafer and (ii) aligned with the gate stack, and then (c) activating the first and second source/drain portions.

5. The method of claim 1, wherein the gate dielectric region comprises a second dielectric material having a dielectric constant greater than 10.

6. The method of claim 1, further comprising:

after said providing the structure is performed but before said causing the first dopants to diffuse is performed, forming a diffusion barrier region (i) on and in direct physical contact with the semiconductor region top surface and (ii) in direct physical contact with the first and second dopant source regions; and

after said causing the first dopants to diffuse is performed but before said forming the gate dielectric region is performed, removing the diffusion barrier region.

7. The method of claim 6, wherein the diffusion barrier region comprises a nitride material.

8. The method of claim 1, further comprising, before said forming the gate dielectric region is performed:

creating first and second contact holes in the first and second dopant source regions, respectively; and

ion implanting second dopants in the semiconductor region via the first and second contact holes so as to form first and second source/drain regions, respectively, wherein the first and second source/drain regions are in direct physical contact with the first and second source/drain extension regions, respectively.

9. The method of claim 8, wherein the first and second source/drain regions have a higher dopant concentration than that of the first and second source/drain extension regions.

10. The method of claim 8, wherein the first dopants and the second dopants have a same dopant polarity.

11. The method of claim 8, further comprising filling the first and second contact holes with an electrically conducting material so as to form first and second contact regions, respectively, wherein the gate region comprises the electrically conducting material.

12. A structure formation method, comprising:

providing a structure including;

(a) a semiconductor region comprising a semiconductor region top surface, and

(b) first and second dopant source regions on and in direct physical contact with the semiconductor region top surface, wherein each region of the first and second dopant source regions comprises a first dielectric material which contains first dopants;

forming a diffusion barrier region (i) on and in direct physical contact with the semiconductor region top surface and (ii) in direct physical contact with the first and second dopant source regions;

causing the first dopants to diffuse from the first and second dopant source regions into the semiconductor region so as to form first and second source/drain extension regions, respectively, in the semiconductor region after said forming the diffusion barrier region is performed,

wherein the first and second source/drain extension regions define a channel region in the semiconductor region, and

wherein the channel region is (i) disposed between and in direct physical contact with the first and second source/drain extension regions and (ii) in direct physical contact with the semiconductor region top surface;

removing the diffusion barrier region after said causing the first dopants to diffuse is performed;

forming a gate dielectric region on the channel region after said removing the diffusion barrier region is performed;

forming a gate region on the gate dielectric region, wherein the gate dielectric region electrically insulates the gate region from the channel region; and

forming first and second contact regions (i) in the first and second dopant source regions, respectively, (ii) not in direct physical contact with the gate region, and (iii) in direct physical contact with the first and second source/drain extension regions, respectively.

13. The method of claim 12, wherein the first dielectric material comprises boron silicate glass.

14. The method of claim 12, wherein the first dielectric material comprises phosphorous silicate glass.

15. The method of claim 12, wherein the gate dielectric region comprises a second dielectric material having a dielectric constant greater than 10.

16. A structure formation method, comprising:

providing a structure including;

(a) a semiconductor region comprising a semiconductor region top surface, and

(b) first, second, third, and fourth dopant source regions on and in direct physical contact with the semiconductor region top surface,

wherein each region of the first and second dopant source regions comprises a first dielectric material which contains first dopants,

wherein each region of the third and fourth dopant source regions comprises a second dielectric material which contains second dopants,

wherein the first and second dopants have opposite dopant polarities, and

wherein the second and third dopant source regions are in direct physical contact with each other;

causing the first dopants to diffuse from the first and second dopant source regions into the semiconductor region so as to form first and second source/drain extension regions, respectively, in the semiconductor region,

wherein the first and second source/drain extension regions define a first channel region in the semiconductor region, and

wherein the first channel region is (i) disposed between and in direct physical contact with the first and second source/drain extension regions and (ii) in direct physical contact with the semiconductor region top surface;

causing the second dopants to diffuse from the third and fourth dopant source regions into the semiconductor region so as to form third and fourth source/drain extension regions, respectively, in the semiconductor region,

wherein the third and fourth source/drain extension regions define a second channel region in the semiconductor region, and

wherein the second channel region is (i) disposed between and in direct physical contact with the third and fourth source/drain extension regions and (ii) in direct physical contact with the semiconductor region top surface, and

wherein the second and third source/drain extension regions are not in direct physical contact with each other;

forming a first gate dielectric region on the first channel region after said causing the first dopants to diffuse and said causing the second dopants to diffuse are performed;

forming a second gate dielectric region on the second channel region after said causing the first dopants to diffuse and said causing the second dopants to diffuse are performed;

forming a first gate region on the first gate dielectric region, wherein the first gate dielectric region electrically insulates the first gate region from the first channel region; and

forming a second gate region on the second gate dielectric region, wherein the second gate dielectric region electrically insulates the second gate region from the second channel region.

17. The method of claim 16,

wherein the first dielectric material comprises boron silicate glass, and

wherein the second dielectric material comprises phosphorous silicate glass.

18. The method of claim 16, wherein the first and second gate dielectric regions comprise a third dielectric material having a dielectric constant greater than 10.

19. The method of claim 16, further comprising:

after said providing the structure is performed but before said causing the first dopants to diffuse and said causing the second dopants to diffuse are performed, forming a diffusion barrier region (i) on and in direct physical contact with the semiconductor region top surface and (ii) in direct physical contact with the first, second, third, and fourth dopant source regions; and

removing the diffusion barrier region after said causing the first dopants to diffuse and said causing the second dopants to diffuse are performed but before said forming the first gate dielectric region and said forming the second gate dielectric region are performed.

20. The method of claim 19, wherein the first gate region comprises a first metal, and wherein the second gate region comprises a second metal different from the first metal.