Method of fabricating a nonvolatile storage array with continuous control gate employing hot carrier injection programming

• US 20070020831A1
• Filed: 07/25/2005
• Published: 01/25/2007
• Est. Priority Date: 07/25/2005
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Chindalore, Gowrishankar, Hong, Cheong, Swift, Craig
• Granted Patent: US 7,314,798 B2
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/42348 with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
• CPC Class Codes: H01L 29/42352 with the gate at least partly formed in a trench
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method of making an array of storage cells includes a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the trenches where the charge storage stack includes a layer of discontinuous storage elements (DSEs). A control gate overlies the first trench. The control gate may run perpendicular to the trenches and traverse the first and second trenches. In another implementation, the control gate runs parallel with the trenches. The storage cell may include one or more diffusion regions occupying an upper surface of the substrate between the first and second trenches. The diffusion region may reside between first and second control gates that are parallel to the trenches. Alternatively, a pair of diffusion regions may occur on either side of a control gate that is perpendicular to the trenches.

Claims

1. A method of fabricating a storage device in an array of storage devices, comprising:

forming first and second trenches in a semiconductor substrate;

forming first and second source/drain regions underlying the first and second trenches respectively;

lining the first and second trenches with a charge storage stack, wherein the charge storage stack include a layer of discontinuous storage elements (DSEs); and

forming a first control gate overlying the first source/drains.

2. The method of claim 1, further comprising forming a first diffusion region between the first and second trenches.

3. The method of claim 2, wherein forming the first control gate includes forming a first control gate running parallel to the first trench.

4. The method of claim 3, further comprising isolating the diffusion region by implanting n+/p+ stripes in the substrate.

5. The method of claim 2, further comprising forming a second diffusion region between the first and second trenches.

6. The method of claim 5, wherein forming the first control gate comprises forming a first control gate perpendicular to the trenches wherein the first control gate traverse the first and second trenches.

7. The method of claim 1, wherein forming the first and second trenches includes forming a dielectric liner on the substrate and a hard mask on the dielectric liner, patterning the dielectric liner and the hard mask;

and etching portion of the substrate exposed by the patterned liner and hard mask.

8. A method of fabricating a storage device in an array of storage devices, comprising:

forming first and second trenches in a semiconductor substrate;

forming first and second source/drain regions underlying the first and second trenches respectively;

lining the first and second trenches with a charge storage stack, wherein the charge storage stack include a layer of discontinuous storage elements (DSEs); and

forming a first control gate overlying the first source/drains;

forming a first diffusion region occupying an upper portion of the substrate between the first and second trenches.

9. The method of claim 8, wherein the first diffusion region contacts metalization only outside of the array.

10. The method of claim 8, wherein forming the first control gate includes forming a first control gate running parallel to the first trench.

11. The method of claim 10, further comprising isolating the diffusion region by implanting alternating n+/p+ stripes in the substrate.

12. The method of claim 8, further comprising forming a second diffusion region between the first and second trenches.

13. The method of claim 12, wherein forming the first control gate comprises forming a first control gate perpendicular to the trenches wherein the first control gate traverse the first and second trenches.

14. The method of claim 8, wherein forming the first and second trenches includes forming a dielectric liner on the substrate and a hard mask on the dielectric liner, patterning the dielectric liner and the hard mask;

and etching portion of the substrate exposed by the patterned liner and hard mask.

15. A method of fabricating a storage device, comprising:

forming a first trench in a semiconductor substrate;

forming a first source/drain region underlying the first trench;

lining the trench with a layer of discontinuous storage elements (DSEs); and

forming a first control gate overlying the first trench.

16. The method of claim 15, wherein forming the first control gate comprises forming the first control gate parallel to the trench.

17. The method of claim 16, further comprising forming a first diffusion region in the substrate between the first control gate and a second control gate overlying the second trench.

18. The method of claim 17, further comprising forming isolation regions by implanting alternating n+ and p+ stripes oriented perpendicular to the trenches.

19. The method of claim 15, wherein forming the first control gate comprises forming the first control gate perpendicular to the trench.

20. The method of claim 18, further comprising forming first and second diffusion region in the substrate, wherein the first diffusion region is on a first side of the first control gate and the second diffusion region is on a second side.