Programmable structure including nanocrystal storage elements in a trench

• US 20070020840A1
• Filed: 07/25/2005
• Published: 01/25/2007
• Est. Priority Date: 07/25/2005
• Status: Abandoned Application

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Chindalore, Gowrishankar
• Application Number:
  US11/188,615
• Publication Number:
  US 20070020840A1
• Time in Patent Office: Days
• US Class Current: 438/211
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/42348 with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
• CPC Class Codes: H01L 29/42352 with the gate at least partly formed in a trench
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A storage cell includes a semiconductor substrate defining a trench, a bottom dielectric lining the trench, and a charge storage layer on the bottom dielectric. The charge storage layer includes a plurality of discontinuous storage elements (DSEs). A control gate and a top dielectric cover the DSEs. The storage cell includes a source/drain region underlying the trench. The DSEs may be silicon nanocrystals and the control gate may be polysilicon. The control gate may be recessed below an upper surface of the semiconductor substrate and an upper most of the DSEs may be vertically aligned with the control gate upper surface. The storage cell may include an oxide gap structure laterally aligned with the silicon nanocrystals adjacent the trench sidewall and extending vertically from the upper most of the silicon nanocrystals to the upper surface of the substrate. The DSEs include at least programmable two injection regions.

Claims

1. A semiconductor fabrication process, comprising:

forming a trench in a semiconductor substrate;

lining the trench with a bottom dielectric;

forming a layer of discontinuous storage elements (DSEs) over the bottom dielectric and a top dielectric over the layer of DSEs;

forming a conductive control gate over the top dielectric; and

forming a source/drain region in the substrate underlying the trench.

2. The method of claim 1, wherein forming the trench includes

depositing an oxide liner on the substrate and a hard mask on the oxide liner;

patterning the oxide liner and the hard mask to expose a portion of the semiconductor substrate; and

etching the exposed portion of the substrate.

3. The method of claim 1, wherein lining the trench comprising thermally oxidizing sidewalls of the trench.

4. The method of claim 1, wherein forming the layer of DSEs comprises forming a layer of silicon nanocrystals.

5. The method of claim 4, wherein forming the top dielectric comprises performing a high temperature oxide process to deposit an oxide on the layer of silicon nanocrystals.

6. The method of claim 1, wherein forming the conductive control gate includes depositing a control gate layer of polysilicon.

7. The method of claim 6, further comprising, etching back the control gate layer to produce a recessed control gate within the trench, wherein an upper surface of the recessed control gate is vertically displaced below an upper surface of the semiconductor substrate.

8. The method of claim 7, further comprising thermally oxidizing an upper portion of the control gate to form a control gate oxide.

9. The method of claim 8, wherein thermally oxidizing an upper portion of the control gate includes oxidizing a portion of the DSEs.

10. A storage cell, comprising;

a semiconductor substrate defining a trench;

a bottom dielectric lining the trench;

a charge storage layer over the bottom dielectric including a plurality of discontinuous storage elements (DSEs);

a top dielectric overlying the layer of DSEs;

a conductive control gate over the top dielectric including at least a portion located in the trench; and

a diffusion region underlying the trench.

11. The storage cell of claim 10, wherein the DSEs comprise silicon nanocrystals.

12. The storage cell of claim 11, wherein the conductive control gate comprises polysilicon;

13. The storage cell of claim 12, further comprising a control gate oxide on the conductive control gate.

14. The storage cell of claim 13, wherein an upper surface of the control gate is vertically displaced below an upper surface of the semiconductor substrate and further wherein an upper most of the polysilicon nanocrystals is vertically aligned approximately to the control gate upper surface.

15. The storage cell of claim 14, further comprising an oxide gap structure laterally aligned with the polysilicon nanocrystals adjacent the trench sidewall and extending vertically from the upper most of the polysilicon nanocrystals to the upper surface of the substrate.

16. The storage cell of claim 10, further comprising a second source/drain region in the substrate, and wherein the layer of DSEs include at least programmable two injection regions wherein biasing the control gate, source/drain regions, and semiconductor substrate in a first biased state programs a first of the injection regions and wherein biasing the control gate, source/drain regions, and semiconductor substrate in a second biased state programs a second of the injection regions.

17. A method of fabricating a storage device, comprising:

forming first and second trenches in a semiconductor substrate;

forming a source/drain regions underlying the first and second trenches;

lining the trenches with a bottom dielectric and a layer of discontinuous storage elements (DSEs) on the bottom dielectric;

forming a top dielectric over the layer of DSEs; and

forming a layer of control gate material in the first and second trenches overlying the top dielectric;

18. The method of claim 17, further comprising forming an oxide gap structure laterally aligned with the DSEs adjacent a sidewall of at least one of the trenches and vertically positioned between an upper most of the DSEs and upper surface of the substrate.

19. The method of claim 18, further comprising forming a control gate oxide overlying the control gate.

20. The method of claim 19, wherein the control gate oxide comprises polysilicon and where forming the oxide gap structure and forming the oxide gap structure occur simultaneously.