Method of fabricating programmable structure including discontinuous storage elements and spacer control gates in a trench

• US 20070020845A1
• Filed: 07/25/2005
• Published: 01/25/2007
• Est. Priority Date: 07/25/2005
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Chindalore, Gowrishankar, Swift, Craig
• Granted Patent: US 7,250,340 B2
• Time in Patent Office: Days
• US Class Current: 438/257
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method of fabricating a semiconductor storage cell that includes first and second source/drain regions underlying first and second trenches defined in a semiconductor substrate. Sidewalls of the trenches are lined with a charge storage stack that includes a layer of discontinuous storage elements (DSEs), which are preferably silicon nanocrystals. Spacer control gates are located in the trenches adjacent to the charge storage stacks on the trench sidewalls. The trench depth exceeds the spacer height so that a gap exists between a top of the spacers and the top of the substrate. A continuous select gate layer overlies the first trench. The gap facilitates ballistic programming of the DSEs adjacent to the gap by accelerating electrons traveling substantially perpendicular to the trench sidewalls. The storage cell may employ hot carrier injection programming to program a portion of the DSEs proximal to the source/drain regions.

Claims

1. A method of fabricating storage device in an array of storage devices, comprising:

forming first and second trenches in a semiconductor substrate;

forming first and second source/drain regions underlying the first and second trenches respectively;

lining sidewalls of the first and second trenches with a charge storage stack, wherein the charge storage stacks include a layer of discontinuous storage elements (DSEs);

forming spacer control gates in the first and second trenches adjacent to the charge storage stacks, wherein a depth of the trenches is greater than a height of the spacer control gates;

forming an isolating dielectric; and

forming a select gate overlying the isolating dielectric and the first trench.

2. The method of claim 1, wherein lining sidewalls of the first and second trenches includes lining the trenches and an upper surface of the substrate with a charge storage stack and anisotropically etching the charge storage stack to remove portions of the charge storage stack from horizontal surfaces.

3. The method of claim 1, wherein the layer of DSEs comprises a layer of silicon nanocrystals formed on a bottom oxide.

4. The method of claim 3, wherein lining the sidewalls includes growing the bottom oxide using thermal oxidation.

5. The method of claim 4, wherein the charge storage stack includes a top oxide adjacent to the layer of DSEs and wherein the top oxide is formed by depositing a high temperature oxide on the DSEs.

6. The method of claim 1, further comprising, prior to forming the control gate spacers, removing the charge storage stack from horizontal surfaces of the substrate and forming a dielectric layer on floors of the trenches.

7. The method of claim 6, wherein forming the control gate spacers comprises forming polysilicon control gate spacers.

8. The method of claim 1, wherein forming the select gate comprises forming a continuous select gate perpendicular and traversing the first and second trenches.

9. The method of claim 8, further comprising forming a first diffusion region occupying an upper portion of the substrate between the first and second trenches.

10. The method of claim 9, further comprising forming a second diffusion region occupying an upper portion of the substrate between the first and second trenches wherein the first diffusion region is located on a first side of the select gate and the second diffusion region is on a second side of the select gate.

11. The method of claim 10, further comprising forming contacts within the array to the first and second diffusion regions.

12. The method of claim 1, wherein forming the select gate comprises forming a select gate overlying and running parallel to the trenches.

13. The method of claim 12, further comprising forming a diffusion region occupying an upper portion of the substrate between the first and second trenches.

14. The method of claim 13, further comprising forming isolation regions bordering opposing sides of the diffusion region.

15. The method of claim 14, wherein forming the isolation regions comprises forming regions of semiconductor substrate having conductivity type opposite of the conductivity type of the diffusion region.

16. The method of claim 13, wherein forming the diffusion region comprises forming a continuous diffusion region extending the array and further comprising forming a contact to the diffusion region outside of the array.

20. The method of claim 1, wherein forming the isolating dielectric comprises depositing a dielectric to fill the first and second trenches and to form a dielectric film on an upper surface of the semiconductor substrate.

17. A method of fabricating a storage device, comprising:

forming a first trench in a semiconductor substrate;

forming a first source/drain region underlying the first trench;

lining the trench sidewall with a layer of discontinuous storage element (DSEs);

forming a first control gate in the trench adjacent to the layer of DSEs, wherein a depth of the trench exceeds a height of the first control gate resulting in a gap over the first control gate between a top of the first control gate and a top of the substrate;

forming an isolating dielectric over the first control gate; and

forming a first select gate overlying the first trench.

18. The method of claim 18, wherein forming the first control gate comprises forming the first control gate parallel to the trench.

19. The method of claim 18, wherein forming the first control gate comprises forming the first control gate perpendicular to the trench.