Hot carrier injection programmable structure including discontinuous storage elements and spacer control gates in a trench and a method of using the same

• US 20070020851A1
• Filed: 09/22/2006
• Published: 01/25/2007
• Est. Priority Date: 07/25/2005
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Li, Chi-Nan, Hong, Cheong
• Granted Patent: US 7,459,744 B2
• Time in Patent Office: Days
• US Class Current: 438/259
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A programmable storage device includes a first diffusion region underlying a portion of a first trench defined in a semiconductor substrate and a second diffusion region occupying an upper portion of the substrate adjacent to the first trench. The device includes a charge storage stack lining sidewalls and a portion of a floor of the first trench. The charge storage stack includes a layer of discontinuous storage elements (DSEs). Electrically conductive spacers formed on opposing sidewalls of the first trench adjacent to respective charge storage stacks serve as control gates for the device. The DSEs may be silicon, polysilicon, metal, silicon nitride, or metal nitride nanocrystals or nanoclusters. The storage stack includes a top dielectric of CVD silicon oxide overlying the nanocrystals overlying a bottom dielectric of thermally formed silicon dioxide. The device includes first and second injection regions in the layer of DSEs proximal to the first and second diffusion regions.

Claims

1. An array of storage cells wherein at least one of the storage cells comprises;

a first diffusion region underlying a portion of a first trench defined in a semiconductor substrate wherein a conductivity type of the first diffusion region is opposite a conductivity type of the substrate;

a second diffusion region occupying an upper portion of the semiconductor substrate adjacent to the first trench wherein a conductivity type of the second diffusion region is opposite the conductivity type of the semiconductor substrate;

a charge storage stack lining sidewalls and a portion of a floor of the first trench wherein the charge storage stack includes a layer of discontinuous storage elements (DSEs); and

electrically conductive spacers formed on sidewalls of the first trench adjacent to respective charge storage stacks.

2. The storage array of claim 1, wherein the DSEs include silicon nanocrystals.

3. The storage array of claim 1, wherein the spacers define a gap overlying the first diffusion region.

4. The storage array of claim 1, wherein the storage cell includes a first injection region within the layer of DSEs proximal to the second diffusion region and a second injection within the layer of DSEs proximal to the first diffusion region.

5. The storage array of claim 4, further comprising a second trench adjacent to the second diffusion region, charge storage stacks lining sidewalls of the second trench and conductive gate spacers adjacent to the charge storage stacks in the second trench and still further comprising a diffusion region underlying a gap defined between the spacers in the second trench.

6. The storage array of claim 1, wherein the DSEs include DSEs underlying the conductive spacers.

7. A method of using a first storage cell within an array of storage cells, the method comprising programming by injecting charge into a first injection region of the first storage cell, including:

biasing a first diffusion region underlying a portion of a first trench in a semiconductor substrate to a fourth programming voltage (V_P4);

biasing a second diffusion region adjacent a charge storage stack including a layer of discontinuous storage elements (DSEs) lining a portion of the first trench to a first programming voltage (V_P1); and

biasing a first conductive spacer within the first trench adjacent to the charge storage stack to a second programming voltage (V_P2).

8. The method of claim 7, wherein the first storage cell is an NMOS device and further wherein V_P1 is approximately 5 V, V_P2 is approximately 6 V, and V_P4 is 0 V (GROUND).

9. The method of claim 7, wherein the first injection region comprises a portion of the DSEs proximal to the second diffusion region.

10. The method of claim 9, further comprising programming a second bit of the first storage cell by injecting charge into a second injection region of the first storage cell by biasing the first diffusion region to V_P1, biasing the conductive spacer to V_P2, and biasing the second diffusion region and the semiconductor substrate to V_P4, wherein the second injection region comprises a portion of the second layer of DSEs proximal to the first diffusion region.

11. The method of claim 10, further comprising injecting charge into a third injection region, wherein the third injection region comprises a portion of a second storage cell within the array of storage cells, by biasing the second diffusion region to V_P1, a second conductive spacer within a second trench to V_P2, wherein the second trench is adjacent to the first diffusion region, and biasing the semiconductor substrate and a third diffusion region underlying a portion of the second trench to V_P4.

12. The method of claim 11, further comprising injecting charge into a fourth injection region, wherein the fourth injection region comprises a portion of a second storage device, by biasing the third diffusion region to V_P1, the second conductive spacer to V_P2, and the semiconductor substrate and the second diffusion region to V_P4.

13. The method of claim 7, further comprising erasing the first storage cell including biasing the first and second control gates to a first erase voltage (V_E1) and biasing the semiconductor substrate to a second erase voltage (V_E2).

14. A method of using an array of storage cells, including a first storage cell, the method comprising:

programming a first bit of the first storage cell by injecting a first set of hot carriers into a first region of the first storage cell, wherein programming the first bit comprises;

biasing a first diffusion region underlying a portion of a first trench in a semiconductor substrate to a first voltage;

biasing a second diffusion adjacent to a first portion of a charge storage stack including a layer of discontinuous storage elements (DSEs) lining a first portion of the first trench to a second voltage that is higher than the first voltage; and

biasing a first conductive spacer within the first trench adjacent to the first portion of the charge storage layer to a third voltage that is greater than each of the first voltage and the second voltage; and

programming a second bit of the first storage cell by injecting a second set of hot carriers into a second region of the first storage cell that is spaced apart from the first region of the first storage cell, wherein programming the second bit comprises;

biasing the first diffusing region to a fourth voltage;

biasing the second diffusion to a fifth voltage that is lower than the fourth voltage; and

biasing the first conductive spacer to a sixth voltage that is greater than each of the fourth voltage and the fifth voltage.

15. The method of claim 14, wherein:

biasing the first diffusion region to the first voltage and biasing the second diffusion region to the fifth voltage are performed such that the first voltage is substantially the same as the fifth voltage; and

biasing the second diffusion region to the second voltage and biasing the first diffusion region to the fourth voltage are performed such that the second voltage is substantially the same as the fourth voltage; and

biasing the first conductive spacer to the third voltage and biasing the first conductive spacer to the sixth voltage are performed such that the third voltage is substantially the same as the sixth voltage.

16. The method of claim 14, wherein and biasing the first diffusion region to the first voltage and biasing the second diffusion region to the fifth voltage are performed such that the first voltage and the fifth voltage are substantially 0 volts.

17. The method of claim 14, further comprising erasing the first bit and the second, wherein erasing comprises:

biasing the first conductive spacer to a seventh voltage; and

biasing a semiconductor substrate lying along a sidewall of the first trench to an eighth voltage that is greater than the seventh voltage.

18. The method of claim 17, wherein biasing the first conductive spacer to the seventh voltage and biasing the semiconductor substrate to the eighth voltage are performed such that the seventh voltage is less than approximately 0 volts, and the eighth voltage is greater than approximately 0 volts.

19. The method of claim 17, wherein:

biasing the first conductive spacer to the seventh voltage and biasing the semiconductor substrate to the eighth voltage are performed such that a first voltage difference is a first absolute value of a first difference between the seventh voltage and the eighth voltage;

biasing the first diffusion region to the first voltage, biasing the second diffusion region to the second voltage, biasing the first conductive spacer to the third voltage, biasing the first diffusing region to the fourth voltage, biasing the second diffusion to the fifth voltage biasing, and the first conductive spacer to the sixth voltage are performed such that a maximum programming voltage difference is a second absolute value of a second difference between any combination of the first voltage, the second voltage, the third voltage, the fourth voltage, the fifth voltage, and the sixth voltage; and

the first absolute value is greater than the second absolute value.

20. The method of claim 14, wherein the array includes a second storage cell, the method further comprising programming a third bit of the second storage cell by injecting a third set of hot carriers into a third region of the second storage cell, wherein programming the third bit comprises:

biasing the first diffusion region to the first voltage;

biasing a third diffusion adjacent to a second portion of the charge storage stack including the layer of DSEs lining a second portion of the first trench to the second voltage; and

biasing a second conductive spacer within the first trench adjacent to the second portion of the second trench to the third voltage.