PCI arbiter
First Claim
1. A method for a bus arbiter to control access to a bus, comprising:
- receiving a bus access request; and
asserting a bus grant associated with the bus access request until an entire packet transfer completion is imminent.
1 Assignment
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Accused Products
Abstract
A bus arbiter that ensures high priority transfers complete and allows high-priority data transfers with specific latency requirements, such as 802.11 requirements, to be prioritized above data transfers with lower latency requirements. As an example, the arbiter closely manages all transactions and guarantees sufficient latencies by pre-empting lower-priority data transfers with higher priority data transfers. All devices on the bus are configured with a latency timer setting of zero or a non-zero value which guarantees required data transfer latencies are met which means that any device will terminate bus-master transfers quickly upon the bus grant signal being de-asserted. To ensure a transfer completes, bus grant for the priority transfer is asserted until entire data transfer completion is imminent, enabling transfers, such as high priority transfers, to complete uninterrupted.
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Citations
26 Claims
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1. A method for a bus arbiter to control access to a bus, comprising:
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receiving a bus access request; and
asserting a bus grant associated with the bus access request until an entire packet transfer completion is imminent. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A system, comprising:
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a bus arbiter coupled to the bus for controlling access to a bus, wherein the bus is coupled to a first device and a second device;
at least one coupler between the bus arbiter and the first device for asserting at least one of the group consisting of a bus access request signal and a bus grant signal between the bus arbiter and the first device; and
at least one coupler between the bus arbiter and the second device for asserting at least one of the group consisting of a bus access request signal and a bus grant signal between the bus arbiter and the second device;
wherein the bus arbiter sets a latency timer for the first device and a latency timer for the second device to zero; and
wherein the bus arbiter is responsive to a bus access request signal from the first device to assert and hold bus grant to the first device until entire data transfer completion is imminent. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A multi-transceiver system, comprising:
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a first wireless transceiver;
a second wireless transceiver;
a host unit comprising a host memory for storing packets for the first wireless transceiver and the second wireless transceiver;
a bus coupling the host processor to the first radio transceiver and the second radio transceiver; and
a bus arbiter for controlling access to the bus, the bus arbiter coupled to the host unit, first wireless transceiver and second wireless transceiver;
wherein the bus arbiter is responsive to a bus access request from the first wireless transceiver to retrieve a packet from the host memory to assert bus grant until the the transfer of entire data packet from host to first wireless receiver is imminent. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23)
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24. A bus arbiter, comprising:
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means for receiving a bus access request from a plurality of devices coupled to the bus; and
means for responding to a bus access request from a one of the plurality of devices coupled to the bus;
wherein the means for responding to a bus access request asserts and holds a bus grant to the one of the plurality of devices coupled to the bus until an initiator ready signal and a target ready signal have been asserted. - View Dependent Claims (25, 26)
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Specification