PCI arbiter

• US 20070022238A1
• Filed: 07/22/2005
• Published: 01/25/2007
• Est. Priority Date: 07/22/2005
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Metsker, Corey
• Granted Patent: US 7,467,245 B2
• Time in Patent Office: Days
• US Class Current: 710/113
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines

Abstract

A bus arbiter that ensures high priority transfers complete and allows high-priority data transfers with specific latency requirements, such as 802.11 requirements, to be prioritized above data transfers with lower latency requirements. As an example, the arbiter closely manages all transactions and guarantees sufficient latencies by pre-empting lower-priority data transfers with higher priority data transfers. All devices on the bus are configured with a latency timer setting of zero or a non-zero value which guarantees required data transfer latencies are met which means that any device will terminate bus-master transfers quickly upon the bus grant signal being de-asserted. To ensure a transfer completes, bus grant for the priority transfer is asserted until entire data transfer completion is imminent, enabling transfers, such as high priority transfers, to complete uninterrupted.

Claims

1. A method for a bus arbiter to control access to a bus, comprising:

receiving a bus access request; and

asserting a bus grant associated with the bus access request until an entire packet transfer completion is imminent.

2. A method according to claim 1, further comprising:

receiving a signal indicative of a priority level corresponding to the bus access request.

3. A method according to claim 2, wherein the signal is received on an unused bus line.

4. A method according to claim 2, wherein the signal is received external to the bus.

5. A method according to claim 2, further comprising:

setting a latency timer to zero;

receiving a second bus access request and a second signal indicative of a priority level corresponding to the second bus access request, wherein the second bus access request is a higher priority than the first bus access request;

de-asserting the bus grant associated with the first bus access request; and

asserting a bus grant to associated with the second bus access request signal.

6. A method according to claim 2, further comprising:

setting a latency timer to zero;

receiving a second bus access request and a second signal indicative of a priority level corresponding to the second bus access request, wherein the second bus access request is a lower priority than the first bus access request;

maintaining the bus grant associated with the first bus access request until a transfer associated with the first bus access request is completed, and then de-asserting the bus grant associated with the first bus access request; and

asserting a bus grant associated with the second bus access request signal after de-asserting bus grant to the initiator of the first bus access request.

7. A method according to claim 1, further comprising:

masking a second bus access request that has a lower priority until a transfer associated with the first bus access request has completed.

8. A method according to claim 1 wherein the bus is one of the group consisting of a PCI version 3.0 compliant bus, a PCI version 2.0 compliant bus, a PCI version 2.1 compliant bus, a PCI version 2.2 complaint bus, a PCI version 2.3 compliant bus a PCI version 1.0 compliant bus, a miniPCI compliant bus and a CardBus compliant bus.

9. A system, comprising:

a bus arbiter coupled to the bus for controlling access to a bus, wherein the bus is coupled to a first device and a second device;

at least one coupler between the bus arbiter and the first device for asserting at least one of the group consisting of a bus access request signal and a bus grant signal between the bus arbiter and the first device; and

at least one coupler between the bus arbiter and the second device for asserting at least one of the group consisting of a bus access request signal and a bus grant signal between the bus arbiter and the second device;

wherein the bus arbiter sets a latency timer for the first device and a latency timer for the second device to zero; and

wherein the bus arbiter is responsive to a bus access request signal from the first device to assert and hold bus grant to the first device until entire data transfer completion is imminent.

10. A system according to claim 9, further comprising:

an additional coupler for coupling the bus arbiter to the first device enabling the bus arbiter to receive a signal indicative of a priority level corresponding to a bus access request from the first device; and

an additional coupler for coupling the bus arbiter to the second device enabling the bus arbiter to receive a signal indicative of a priority level corresponding to a bus access request from the second device.

11. A system according to claim 10, further comprising:

the bus arbiter responsive to receiving a second bus access request on the at least one coupler between the bus arbiter and the second device for asserting bus request and bus signals between the bus arbiter and the second device and a second signal indicative of a priority level corresponding to the second bus access request on the additional coupler for coupling the bus arbiter to the second device enabling the bus arbiter to receive a signal indicative of a priority level corresponding to a bus access request from the second device, wherein the second bus access request is a higher priority than the first bus access request, to de-assert bus grant to the first device, and assert a bus grant to the second device.

12. A system according to claim 11, wherein the first device is responsive to relinquish the bus as soon as bus grant to the first device is de-asserted.

13. A system according to claim 10, further comprising:

the arbiter responsive to receiving a second bus access request on the at least one coupler between the bus arbiter and the second device for asserting bus request and bus signals between the bus arbiter and the second device and a second signal indicative of a priority level corresponding to the second bus access request on the additional coupler for coupling the bus arbiter to the second device enabling the bus arbiter to receive a signal indicative of a priority level corresponding to a bus access request from the second device, wherein the second bus access request is a lower priority than the first bus access request, to continue asserting bus grant to the first device until a transfer associated with the first bus access request is completed and asserting a bus grant to the second device after de-asserting bus grant the first device.

14. A system according to claim 9, further comprising a circuit for masking a second bus access request that has a lower priority until a transfer associated with the first bus access request has completed.

15. A system according to claim 9, wherein the bus is one of the group consisting of a PCI version 3.0 compliant bus, a PCI version 2.0 compliant bus, a PCI version 2.1 compliant bus, a PCI version 2.2 complaint bus, a PCI version 2.3 compliant bus a PCI version 1.0 compliant bus, a miniPCI compliant bus and a CardBus compliant bus.

16. A multi-transceiver system, comprising:

a first wireless transceiver;

a second wireless transceiver;

a host unit comprising a host memory for storing packets for the first wireless transceiver and the second wireless transceiver;

a bus coupling the host processor to the first radio transceiver and the second radio transceiver; and

a bus arbiter for controlling access to the bus, the bus arbiter coupled to the host unit, first wireless transceiver and second wireless transceiver;

wherein the bus arbiter is responsive to a bus access request from the first wireless transceiver to retrieve a packet from the host memory to assert bus grant until the the transfer of entire data packet from host to first wireless receiver is imminent.

17. A multi-transceiver system according to claim 16, further comprising:

the first wireless transceiver further comprising a latency timer; and

the second wireless transceiver further comprising a latency timer;

wherein the bus arbiter sets a latency timer for the first wireless transceiver and the latency timer for the second wireless transceiver to zero; and

the first wireless transceiver and second wireless transceiver are responsive to the latency timer being set to zero to relinquish the bus immediately after the bus arbiter de-asserts bus grant.

18. A multi-transceiver system according to claim 16, further comprising:

the host unit further comprising a buffer coupled to the bus;

wherein the host unit does not indicate it is ready to send the packet until the packet is transferred from the host memory to the buffer.

19. A multi-transceiver system according to claim 18, further comprising:

a central processing unit; and

a second bus coupling the central processing unit, host memory and buffer;

wherein the central processing unit processes the packet prior to the packet being stored in the buffer.

20. A multi-transceiver system according to claim 19, further comprising an interface to a distribution system;

wherein the interface receives the packet from the distribution system and stores the packet in the host memory.

21. A multi-transceiver system according to claim 16, further comprising:

a first priority communications link between the first wireless transceiver and the bus arbiter for indicating a priority level associated with a bus request initiated by the first wireless transceiver; and

a second priority communications link between the second wireless transceiver and the bus arbiter for indicating a priority level associated with a bus request initiated by the second wireless transceiver.

22. The multi-transceiver system according to claim 21, further comprising:

the bus arbiter receiving a priority level on the first priority communications link indicative of a priority level of the bus request from the first wireless transceiver;

the bus arbiter receiving a bus access request from the second wireless transceiver and a priority level for the bus access request from the second wireless transceiver on the second priority communications link indicative of the priority level of the bus request from the second wireless transceiver;

wherein the bus arbiter is responsive to the priority level of first wireless transceiver being greater than the priority level of the second wireless transceiver to continue asserting bus grant to the first wireless transceiver until a response to the bus request from the first wireless transceiver has been completed.

23. The multi-transceiver system according to claim 21, further comprising:

the bus arbiter receiving a priority level on the first priority communications link indicative of a priority level of the bus request from the first wireless transceiver;

the bus arbiter receiving a bus access request from the second wireless transceiver and a priority level for the bus access request from the second wireless transceiver on the second priority communications link indicative of the priority level of the bus request from the second wireless transceiver;

wherein the bus arbiter is responsive to the priority level of second wireless transceiver being greater than the priority level of the first wireless transceiver to immediately de-assert bus grant to the first wireless transceiver and assert bus grant to the second wireless transceiver.

24. A bus arbiter, comprising:

means for receiving a bus access request from a plurality of devices coupled to the bus; and

means for responding to a bus access request from a one of the plurality of devices coupled to the bus;

wherein the means for responding to a bus access request asserts and holds a bus grant to the one of the plurality of devices coupled to the bus until an initiator ready signal and a target ready signal have been asserted.

25. A bus arbiter according to claim 24, further comprising means for setting a latency timer corresponding to the plurality of devices coupled to the bus to zero.

26. A bus arbiter according to claim 25, further comprising:

means for determining a priority level associated with the bus access request from the plurality of devices coupled to the bus; and

means for de-asserting bus grant responsive to the means for determining a priority level after a second of the plurality of devices initiates a bus grant request with a higher level than the one of the plurality of devices coupled to the bus.