Compressing and accessing a microcode ROM

• US 20070022279A1
• Filed: 07/20/2005
• Published: 01/25/2007
• Est. Priority Date: 07/20/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wu, Youfeng, Hum, Herbert, Breternitz, Mauricio, Kim, Sangwook
• Granted Patent: US 8,099,587 B2
• Time in Patent Office: Days
• US Class Current: 712/245
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 2212/401 Compressed data
• CPC Class Codes: G06F 8/4436 Exlining; Procedural abstraction
• CPC Class Codes: G06F 9/30178 of compressed or encrypted instructions

Abstract

An arrangement is provided for compressing microcode ROM (“uROM”) in a processor and for efficiently accessing a compressed “uROM”. A clustering-based approach may be used to effectively compress a uROM. The approach groups similar columns of microcode into different clusters and identifies unique patterns within each cluster. Only unique patterns identified in each cluster are stored in a pattern storage. Indices, which help map an address of a microcode word (“uOP”) to be fetched from a uROM to unique patterns required for the uOP, may be stored in an index storage. Typically it takes a longer time to fetch a uOP from a compressed uROM than from an uncompressed uROM. The compressed uROM may be so designed that the process of fetching a uOP (or uOPs) from a compressed uROM may be fully-pipelined to reduce the access latency.

Claims

1. An apparatus for storing computing code and providing access to said code, comprising:

a pattern storage to store unique patterns identified in said code;

an index storage to store indices of said unique patterns stored in said pattern storage; and

a controller to enable a process of accessing said index storage and said pattern storage to obtain a code word to be pipelined.

2. The apparatus of claim 1, further comprising an index buffer to temporarily store indices retrieved from said index storage by an address of a code word to be fetched.

3. The apparatus of claim 1, wherein said process of accessing said index storage and said pattern storage to produce a code word comprises:

receiving an address of a code word to be fetched by said index storage;

obtaining indices of unique patterns required to produce said code word from said index storage; and

fetching said required unique patterns from said pattern storage to produce said code word.

4. The apparatus of claim 1, wherein said pattern storage comprises one or more sections, each section storing unique patterns for a group of columns in said code.

5. The apparatus of claim 4, wherein said index storage comprises one or more sections, each section corresponding to a section in said pattern storage to store indices of patterns stored in the section in said pattern storage.

6. The apparatus of claim 1, wherein said index storage and said pattern storage are capable of being accessed by addresses of multiple code words in parallel.

7. A processor, comprising:

at least one processing core;

a microcode read only memory (“

uROM”

) to store microcode, said uROM including;

a pattern storage to store unique patterns identified in said microcode, and

an index storage to store indices of said unique patterns stored in said pattern storage; and

a control mechanism to enable said at least one processing core to pipeline a process of accessing said uROM to obtain a microcode word (“

uOP”

).

8. The processor of claim 7, wherein said UROM further comprises an index buffer to temporarily store indices retrieved from said index storage by an address of a uOP to be fetched.

9. The processor of claim 7, wherein said process of accessing said UROM to produce a uOP comprises:

receiving an address of a uOP to be fetched by said index storage;

obtaining indices of unique patterns required to produce said uOP from said index storage; and

fetching said required unique patterns from said pattern storage to produce said uOP.

10. The processor of claim 7, wherein said pattern storage comprises one or more sections, each section storing unique patterns for a group of columns in said microcode;

and said index storage comprises one or more sections, each section corresponding to a section in said pattern storage to store indices of patterns stored in the section in said pattern storage.

11. The processor of claim 7, wherein said at least one processing core comprises said control mechanism.

12. The processor of claim 7, wherein said uROM is capable of being accessed by multiple uOP addresses in parallel.

13. A computing system, comprising:

at least one processor; and

a system interconnect to couple said at least one processor together;

wherein said at least one processor includes;

at least one processing core;

a microcode read only memory (“

uROM”

) to store microcode; and

a control mechanism to enable said at least one processing core to pipeline a process of accessing said uROM to obtain a microcode word (“

uOP”

).

14. The system of claim 13, wherein said uROM comprises:

a pattern storage to store unique patterns identified in said microcode; and

an index storage to store indices of said unique patterns stored in said pattern storage.

15. The system of claim 14, wherein said uROM further comprises an index buffer to temporarily store indices retrieved from said index storage by an address of a uOP to be fetched.

16. The system of claim 14, wherein said process of accessing said uROM to produce a uOP comprises:

receiving an address of a uOP to be fetched by said index storage;

obtaining indices of unique patterns required to produce said uOP from said index storage; and

fetching said required unique patterns from said pattern storage to produce said uOP.

17. The system of claim 14, wherein said pattern storage comprises one or more sections, each section storing unique patterns for a group of columns in said microcode;

and said index storage comprises one or more sections, each section corresponding to a section in said pattern storage to store indices of patterns stored in the section in said pattern storage.

18. The system of claim 14, wherein said at least one processing core comprises said control mechanism.

19. The system of claim 13, wherein said uROM is capable of being accessed by multiple uOP addresses in parallel.

20. A method for accessing a microcode read only memory (“

uROM”

) that is at least partly compressed, comprising;

receiving an address of a microcode word (“

uOP”

) to be fetched from said uROM;

determining whether said uOP is stored in an uncompressed portion of said uROM, based at least in part on said received address;

if said uOP is stored in said uncompressed portion,

fetching said uOP from said uncompressed portion directly based on said received address;

otherwise,

fetching said uOP from a compressed portion of said UROM through a pipelined process.

21. The method of claim 20, wherein said compressed portion of said uROM comprises:

a pattern storage to store unique patterns identified in said microcode;

an index storage to store indices of said unique patterns stored in said pattern storage; and

an index buffer to temporarily store indices retrieved from said index storage by an address of a uOP to be fetched.

22. The method of claim 21, wherein said pipelined process for fetching a uOP from said compressed portion of said uROM comprises:

fetching indices of unique patterns required to produce said uOP from said index storage based at least in part on said received address;

fetching said required unique patterns from said pattern storage according to said fetched indices; and

producing said uOP based at least in part on said fetched required unique patterns.

23. The method of claim 22, wherein said pipelined process further comprises temporarily storing said fetched indices in said index buffer before fetching said required unique patterns from said pattern storage.

24. The method of claim 22, wherein said indices of unique patterns required to produce said uOP are fetched from said index storage in parallel.

25. The method of claim 22, wherein said required unique patterns are fetched from said pattern storage in parallel.

26. The method of claim 20, wherein said uncompressed portion and said compressed portion of said uROM are capable of being accessed by multiple uOP addresses in parallel.