Systems, methods and computer programs for calibrating an automated circuit test system

• US 20070022347A1
• Filed: 06/27/2005
• Published: 01/25/2007
• Est. Priority Date: 06/27/2005
• Status: Active Grant

• Current Assignee: Verigy Limited (Advantest Corporation)
• Original Assignee: Verigy Limited (Advantest Corporation)
• Inventors: Sugihara, Noriyuki
• Granted Patent: US 7,281,181 B2
• Time in Patent Office: Days
• US Class Current: 714/735
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 35/005 Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references G01R33/0035, G01R35/002 take precedence

Abstract

In one embodiment, an automated circuit test system is calibrated by electrically coupling a first calibration unit between a plurality of drivers and comparators of the test system, and then executing an AC timing calibration procedure to determine a timing delay for each of a first set of relationships. A second calibration unit is then electrically coupled between the plurality of drivers and comparators, and an AC timing calibration procedure is executed to determine a timing delay for each of a second set of relationships. The first and second calibration units comprise fixed wiring paths that respectively couple pairs of the drivers and comparators in accord with the first and second sets of relationships. A set of equations is solved based on the timing delays and driver/comparator relationships to determine relative timing errors introduced by signal paths of the test system including the drivers and comparators.

Claims

1. A method for calibrating an automated circuit test system, comprising:

electrically coupling a first calibration unit between a plurality of drivers and comparators of the test system, the first calibration unit comprising fixed wiring paths that couple pairs of the drivers and comparators in accord with a first set of relationships;

executing an AC timing calibration procedure while the first calibration unit is coupled between the plurality of drivers and comparators, thereby determining a timing delay for each of the first set of relationships;

electrically coupling a second calibration unit between the plurality of drivers and comparators, the second calibration unit comprising fixed wiring paths that couple pairs of the drivers and comparators in accord with a second set of relationships;

executing an AC timing calibration procedure while the second calibration unit is coupled between the plurality of drivers and comparators, thereby determining a timing delay for each of the second set of relationships; and

solving a set of equations based on the timing delays and driver/comparator relationships to determine i) relative timing errors introduced by signal paths of the test system that include the drivers, and ii) relative timing errors introduced by signal paths of the test system that include the comparators.

2. The method of claim 1, wherein the set of equations is solved, in part, by setting a timing error associated with a reference one of the signal paths including one of the drivers to a default value.

3. The method of claim 2, wherein the default value is zero.

4. The method of claim 1, wherein the set of equations is solved, in part, by setting a timing error associated with a reference one of the signal paths including one of the comparators to a default value.

5. The method of claim 4, wherein the default value is zero.

6. The method of claim 1, further comprising, placing the calibration units between the plurality of drivers and comparators, and removing the calibration units from between the plurality of drivers and comparators, using a robotic system.

7. A system for calibrating an automated circuit test system, comprising:

first and second calibration units, each comprising i) a driver interface having multiple driver contacts for electrically coupling the calibration unit to a plurality of drivers of the test system, ii) a comparator interface having multiple comparator contacts for electrically coupling the calibration unit to a plurality of comparators of the test system, and iii) a plurality of fixed wiring paths coupling pairs of the calibration unit'"'"'s driver contacts and comparator contacts;

wherein the fixed wiring paths of the first calibration unit couple pairs of the calibration unit'"'"'s driver and comparator contacts in accord with a first set of relationships, and wherein the fixed wiring paths of the second calibration unit couple pairs of the second calibration unit'"'"'s driver and comparator contacts in accord with a second set of relationships.

8. The system of claim 7, wherein the calibration units comprise alumina substrates on which the fixed wiring paths are deposited.

9. The system of claim 8, wherein the fixed wiring paths are thin film circuit traces.

10. The system of claim 7, wherein the calibration units comprise printed circuit boards.

11. The system of claim 7, wherein the fixed wiring paths comprise coaxial cables.

12. The system of claim 7, wherein the calibration units are sized to mimic actual devices under test that will be tested by the test system after the test system is calibrated using the calibration units.

13. The system of claim 7, wherein the calibration units are shaped to mimic wafers that will be tested by the test system after the test system is calibrated using the calibration units.

14. A computer program for calibrating an automated circuit test system, comprising:

code to initiate a first AC timing calibration procedure while a first calibration unit is electrically coupled between a plurality of drivers and comparators of the test system, wherein the first calibration unit comprises fixed wiring paths that couple pairs of the drivers and comparators in accord with a first set of relationships, and wherein the first AC timing calibration procedure determines a timing delay for each of the first set of relationships;

code to initiate a second AC timing calibration procedure while a second calibration unit is electrically coupled between the plurality of drivers and comparators, wherein the second calibration unit comprising fixed wiring paths that couple pairs of the drivers and comparators in accord with a second set of relationships, and wherein the second AC timing calibration procedure determines a timing delay for each of the second set of relationships; and

code to solve a set of equations based on the timing delays and driver/comparator relationships to determine relative timing errors between the drivers and relative timing errors between the comparators.

15. The computer program of claim 14, wherein the code solves the set of equations, in part, by setting a timing error associated with a reference one of the signal paths including one of the drivers to a default value.

16. The computer program of claim 15, wherein the default value is zero.

17. The computer program of claim 14, wherein the code solves the set of equations, in part, by setting a timing error associated with a reference one of the signal paths including one of the comparators to a default value.

18. The computer program of claim 17, wherein the default value is zero.

19. A method for calibrating an automated circuit test system, comprising:

electrically coupling a first calibration unit between a plurality of drivers and comparators of the test system, the first calibration unit comprising fixed wiring paths that couple pairs of the drivers and comparators in accord with a first set of relationships;

executing a resistance check while the first calibration unit is coupled between the plurality of drivers and comparators, thereby determining resistances for signal paths defined by the first set of relationships;

electrically coupling a second calibration unit between the plurality of drivers and comparators, the second calibration unit comprising fixed wiring paths that couple pairs of the drivers and comparators in accord with a second set of relationships;

executing a resistance check while the second calibration unit is coupled between the plurality of drivers and comparators, thereby determining resistances for signal paths defined by the second set of relationships; and

solving a set of equations based on the resistances and driver/comparator relationships to determine i) relative resistances imparted by signal paths of the test system that include the drivers, and ii) relative resistances imparted by signal paths of the test system that include the comparators.

20. The method of claim 19, wherein the set of equations is solved, in part, by i) setting a resistance associated with a reference one of the signal paths including one of the drivers to a default value, and ii) setting a resistance associated with a reference one of the signal paths including one of the comparators to a default value.