System and method for lithography simulation

• US 20070022402A1
• Filed: 09/26/2006
• Published: 01/25/2007
• Est. Priority Date: 10/07/2003
• Status: Active Grant

• Current Assignee: ASML Netherlands BV (ASML Holding NV)
• Original Assignee: ASML Netherlands BV (ASML Holding NV)
• Inventors: Ye, Jun, Chen, Luoqi, Chen, Xun, Lu, Yen-Wen, Cao, Yu
• Granted Patent: US 7,873,937 B2
• Time in Patent Office: Days
• US Class Current: 716/52
• CPC Class Codes: G03F 1/00 Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
• CPC Class Codes: G03F 7/004 Photosensitive materials G03F7/12, G03F7/14 take precedence
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70666 Aerial image, i.e. measuring the image of the patterned exposure light at the image plane of the projection system
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/333 Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0004 Industrial image inspection
• CPC Class Codes: G16Z 99/00 Subject matter not provided for in other main groups of this subclass
• CPC Class Codes: G21K 5/00 Irradiation devices discharge tubes for irradiating H01J37/00

Abstract

There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.

Claims

1-35. -35. (canceled)

36. A system to simulate a lithographic design comprised of a plurality of polygons arranged in a predetermined configuration, the system comprising:

a microprocessor subsystem to convert a circuit design database, which is representative of a integrated circuit pattern, to a pixel-based bitmap representation thereof, wherein the pixel-based bitmap includes pixel data; and

an accelerator subsystem, coupled to the microprocessor subsystem, to calculate at least a portion of an aerial image of the lithographic design using the pixel-based bitmap representation of the lithographic design.

37. The system of claim 36, further including a plurality of accelerator subsystems, wherein each accelerator subsystem is coupled to the microprocessor subsystem and provided a portion of the pixel-based bitmap to calculate an aerial image of the lithographic design corresponding to the portion of the pixel-based bitmap using the pixel data associated therewith.

38. The system of claim 36, wherein, the circuit design database includes a plurality of polygons arranged in a predetermined pattern.

39. The system of claim 36, wherein, the accelerator subsystem further includes a plurality of programmable gate arrays configured to process the pixel data in parallel.

40. The system of claim 36, wherein the lithographic design includes resolution enhancement technology and wherein the microprocessor subsystem converts a plurality of polygons, including resolution enhancement technology, to a pixel-based bitmap representation thereof.

41. The system of claim 36, wherein the microprocessor subsystem includes a plurality of microprocessors and wherein each microprocessor is coupled to at least one associated accelerator subsystem.

42. The system of claim 36, wherein the accelerator subsystem calculates an aerial image in resist formed on a wafer by the lithographic design, and wherein the accelerator subsystem calculates the aerial image in resist using the pixel-based bitmap representation of the lithographic design and a coefficient matrix representing projection and illumination optics of a photolithographic tool.

43. The system of claim 42, wherein the accelerator subsystem calculates a pattern formed on the wafer by the lithographic design.

44. The system of claim 43, further including a processing system, coupled to the microprocessor subsystem and the accelerator subsystem, to compare the calculated pattern on the wafer to a desired, predetermined pattern.

45. The system of claim 43, further including a processing system, coupled to the microprocessor subsystem and the accelerator subsystem, to determine a critical dimension (CD) of the lithographic design using the calculated pattern on the wafer.

46. The system of claim 43, further including a processing system, coupled to the microprocessor subsystem and the accelerator subsystem, to determine an edge placement of the lithographic design using the calculated pattern on the wafer.

47. The system of claim 43, further including a processing system, coupled to the microprocessor subsystem and the accelerator subsystem, to determine a printing sensitivity using patterns on the wafer calculated in response to varying coefficients of the matrix representing projection and illumination optics of a photolithographic tool.

48. The system of claim 47, wherein the coefficients of the matrix representing projection and illumination optics of a photolithographic tool are representative of one or more of a focus, dose, numerical aperture, illumination aperture, and aberration.

49. The system of claim 48, wherein the processing system determines a set of parameters of the projection and illumination optics of a photolithographic tool using the printing sensitivity.

50. The system of claim 43, further including a processing system, coupled to the microprocessor subsystem and the accelerator subsystem, to detect an error in the lithographic design in response to a comparison between the calculated pattern on the wafer and a desired, predetermined pattern.

51. The system of claim 50, wherein, in response to detecting the error, the processing system determines a modification to the lithographic design to correct the error in the lithographic design.

52. A system for simulating a lithographic design, the system comprising:

means for partitioning a database which includes information which is representative of the lithographic design;

means for converting the lithographic design to a pixel-based bitmap representation thereof, wherein the pixel-based bitmap includes pixel data, and wherein each pixel datum represents a pixel having a predetermined pixel size, wherein the lithographic design includes resolution enhancement technology; and

means for calculating a portion of an aerial image of the lithographic design using a corresponding portion of the pixel-based bitmap representation of the lithographic design.

53. The system of claim 52, wherein the lithographic design includes a plurality of polygons arranged in a predetermined configuration.

54. The system of claim 53, wherein the pixel-based bitmap includes a gray-level image which is representative of the plurality of polygons.

55. The system of claim 52, wherein the means for calculating a portion of an aerial image of the lithographic design further calculates an aerial image in resist formed on a wafer by the lithographic design using the pixel-based bitmap representation of the lithographic design and a coefficient matrix representing projection and illumination optics of a photolithographic tool.

56. The system of claim 52, wherein the means for calculating a portion of an aerial image of the lithographic design further calculates a pattern formed on a wafer by the lithographic design using the pixel-based bitmap representation of the lithographic design and the coefficient matrix representing projection and illumination optics of a photolithographic tool.

57. The system of claim 56, further including means for comparing the calculated pattern on the wafer to a desired, predetermined pattern.

58. A system to simulate a lithographic design comprised of a plurality of polygons arranged in a predetermined configuration, the system comprising:

a microprocessor computing system to;

(1) convert the plurality of polygons to a pixel-based bitmap representation thereof, wherein the pixel-based bitmap includes pixel data, and wherein each pixel datum represents a pixel having a predetermined pixel size,

(2) calculate at least a portion of an aerial image of the lithographic design using the pixel-based bitmap representation of the lithographic design, and

(3) calculate a pattern formed on a wafer by the lithographic design using the pixel-based bitmap representation of the lithographic design and a coefficient matrix representing projection and illumination optics of a photolithographic tool; and

a processing system, coupled to the microprocessor computing system, to determine a printing sensitivity using patterns on the wafer calculated in response to varying coefficients of the matrix representing projection and illumination optics of a photolithographic tool.

59. The system of claim 58, wherein the processing system, further determines a critical dimension (CD) of the lithographic design using the calculated pattern on the wafer.

60. The system of claim 58, wherein the processing system, further determines an edge placement of the lithographic design using the calculated pattern on the wafer.

61. The system of claim 58, wherein the coefficients of the matrix representing projection and illumination optics of a photolithographic tool are representative of one or more of a focus, dose, numerical aperture, illumination aperture, and aberration.

62. The system of claim 58, wherein the processing system further determines a set of parameters of the projection and illumination optics of a photolithographic tool using the printing sensitivity.

63. The system of claim 58, wherein the processing system detects an error in the lithographic design in response to a comparison between the calculated pattern on the wafer and a desired, predetermined pattern.

64. The system of claim 58, wherein, in response to detecting the error, the processing system further determines a modification to the lithographic design to correct the error in the lithographic design.

65. A system to simulate a lithographic design comprised of a plurality of polygons arranged in a predetermined configuration, the system comprising:

a microprocessor computing system to;

(1) convert the plurality of polygons to a pixel-based bitmap representation thereof, wherein the pixel-based bitmap includes pixel data, and wherein each pixel datum represents a pixel having a predetermined pixel size,

(2) calculate an aerial image in resist formed on a wafer by the lithographic design using the pixel-based bitmap representation of the lithographic design and a coefficient matrix representing projection and illumination optics of a photolithographic tool, and

(3) calculate a pattern formed on a wafer by the lithographic design using the pixel-based bitmap representation of the lithographic design and a coefficient matrix representing projection and illumination optics of a photolithographic tool; and

a processing system, coupled to the microprocessor computing system, to determine a printing sensitivity using patterns on the wafer calculated in response to varying coefficients of the coefficient matrix representing projection and illumination optics of a photolithographic tool.

66. The system of claim 65, wherein the processing system further determines a critical dimension (CD) of the lithographic design using the calculated pattern on the wafer.

67. The system of claim 65, wherein the processing system further determines an edge placement of the lithographic design using the calculated pattern on the wafer.

68. The system of claim 65, wherein the coefficients of the matrix representing projection and illumination optics of a photolithographic tool are representative of one or more of a focus, dose, numerical aperture, illumination aperture, and aberration.

69. The system of claim 65, wherein the processing system further determines a set of parameters of the projection and illumination optics of a photolithographic tool using the printing sensitivity.

70. The system of claim 65, wherein the processing system detects an error in the lithographic design in response to a comparison between the calculated pattern on the wafer and a desired, predetermined pattern.

71. The system of claim 65, wherein, in response to detecting the error, the processing system further determines a modification to the lithographic design to correct the error in the lithographic design.