Context switching method, device, program, recording medium, and central processing unit

• US 20070022428A1
• Filed: 12/11/2003
• Published: 01/25/2007
• Est. Priority Date: 01/09/2003
• Status: Active Grant

• Current Assignee: Japan Science & Technology Trading Co. Limited
• Original Assignee: Japan Science & Technology Trading Co. Limited
• Inventors: Yamasaki, Nobuyuki
• Granted Patent: US 8,020,169 B2
• Time in Patent Office: Days
• US Class Current: 718/108
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/461 Saving or restoring of program or task context

Abstract

In an application in which context switching often occurs such as in a real time OS, it is possible to significantly reduce the overhead caused by the context switching. The OS issues a Swap instruction and a context switch starts. The Swap instruction is issued together with a thread (i.e., context) ID to be replaced, to a thread control unit (9). The thread ID is used to uniquely identify threads stored in a context cache (8). The thread control unit (9) saves data from a register file (1) to the context cache (8) via a context-dedicated bus (12) and transmits data of a new thread from the context cache (8) to the register file (1). According to the thread ID received, the thread control unit (9) automatically interchanges the necessary number of data in the register file (1) and the data in the context cache (8).

Claims

1. A context switching unit for switching a plurality of contexts, the context switching unit comprising:

a register file having stored a context related to a thread to be executed by an arithmetic logic unit or a memory access unit, the register file comprising a read port, a write port, a context-switching read port, and a context-switching write port;

a context cache for caching a context, the context cache comprising a read port and a write port, being connected directly to the register file, and being contained in a central processing unit in a on-chip manner;

a context switching bus for connecting the register file and the context cache, the context switching bus comprising a restore bus and a save bus for connecting the read port and the write port of the context cache to the context-switching write port and the context-switching read port of the register file respectively; and

a thread control unit for controlling data transfer between the context cache and the register file, the thread control unit comprising a thread identifier table for storing a thread identifier for identifying the context of a thread stored in the context cache and being connected in parallel with the arithmetic logic unit and the memory access unit, wherein the thread control unit receives a context switch instruction for executing a save operation and a restore operation concurrently and the identifier of a new thread to be interchanged, when a context switch which executes both a context save operation and a context restore operation in parallel occurs;

the thread control unit obtains a restore address where a new context to be interchanged is stored in the context cache and the save register identifier indicating the location where the current context is stored in the register file, by searching through the thread identifier table in accordance with the thread identifier;

the thread control unit sends the obtained address to the context cache and sends the register identifier to the register file concurrently;

the register file, in accordance with the register identifier given by the thread control unit, outputs the data of the context to be saved from the context-switching read port and, concurrently writes the data of the context to be restored, sent from the read port of the context cache to the context-switching write port through the restore bus, in the register corresponding to the register identifier;

the context cache, in accordance with the address given by the thread control unit, outputs the data of the context to be restored from the read port and, concurrently writes the data of the context to be saved sent from the context-switching read port of the register file to the write port via the save bus; and

the context switching unit switches contexts by executing an operation for restoring a context from the context cache to the register file and an operation for saving a context from the register file to the context cache concurrently.

2. The context switching unit according to claim 1, wherein the context switching bus has a bus width greater than the bit width of the register file.

3. The context switching unit according to claim 1, wherein the thread control unit comprises as many thread identifier tables as required to identify contexts cached in the context cache.

5. The context switching unit according to claim 1, wherein the thread control unit saves the context of the current thread from the register file to the context cache and sends the context of a new thread from the context cache to the register file concurrently to automatically interchange a required number of data items between the register file and the context cache, when software, such as an operating system, issues a swap instruction for interchanging contexts, including a thread identifier as an operand, if the swap instruction is executed.

6. The context switching unit according to claim 1, wherein the thread control unit transfers the data of a context from the register file to the context cache and does not transfer the data of a context from the context cache to the register file, when software, such as an operating system, issues a backup instruction for saving a context, including a thread identifier as an operand, if the backup instruction is executed.

7. The context switching unit according to claim 1, wherein the thread control unit transfers the data of a context from the context cache to the register file and does not transfer the data of a context from the register file to the context cache, when software, such as an operating system, issues a restore instruction for restoring a context, including a thread identifier as an operand, if the restore instruction is executed.

8. A central processing unit comprising:

a context switching unit according to claim 1;

an instruction cache for caching an instruction and a data cache for caching data;

an instruction fetch unit for fetching an instruction from the instruction cache and decoding the instruction;

an arithmetic logic unit for performing an operation in accordance with an instruction stored in the register file and writing the result of the operation back in the register file;

a memory access unit for receiving an operand and an instruction from the register file, accessing the data cache, and executing a load or store operation; and

an arithmetic bus for connecting the register file, the arithmetic logic unit, the memory access unit, and the thread control unit in parallel.

9. The central processing unit according to claim 8, wherein the memory access unit sends an address and data to the data cache and stores the data in the data cache when a store instruction is given, and the memory access unit sends an address to the data cache, reads data from the data cache, and writes the read data back into the register file when a load instruction is given.

4. (canceled)

10. A context switching method for switching a plurality of contexts by using a context switching unit comprising:

storing a context related to a thread in a register file to be executed by an arithmetic logic unit or a memory access unit, the register file comprising a read port, a write port, a context-switching read port, and a context-switching write port;

caching a context, in a context cache the context cache comprising a read port and a write port, being connected directly to the register file, and being contained in a central processing unit in a on-chip manner;

connecting the register file and the context cache with a context switching bus, the context switching bus comprising a restore bus and a save bus for connecting the read port and the write port of the context cache to the context-switching write port and the context-switching read port of the register file respectively; and

controlling data transfer between the context cache and the register file using a thread control unit, the thread control unit comprising a thread identifier table for storing a thread identifier for identifying the context of a thread stored in the context cache and being connected in parallel with the arithmetic logic unit and the memory access unit,

wherein the thread control unit receives a context switch instruction for executing a save operation and a restore operation concurrently and the identifier of a new thread to be interchanged, when a context switch which executes both a context save operation and a context restore operation in parallel occurs;

the thread control unit obtains a restore address where a new context to be interchanged is stored in the context cache and the save register identifier indicating the location where the current context is stored in the register file, by searching through the thread identifier table in accordance with the thread identifier;

the thread control unit sends the obtained address to the context cache and sends the register identifier to the register file concurrently;

the register file, in accordance with the register identifier given by the thread control unit, outputs the data of the context to be saved from the context-switching read port and, concurrently writes the data of the context to be restored, sent from the read port of the context cache to the context-switching write port through the restore bus, in the register corresponding to the register identifier;

the context cache, in accordance with the address given by the thread control unit, outputs the data of the context to be restored from the read port and, concurrently writes the data of the context to be saved sent from the context-switching read port of the register file to the write port via the save bus; and

the context switching unit switches contexts by executing an operation for restoring a context from the context cache to the register file and an operation for saving a context from the register file to the context cache concurrently.

11. The context switching method according to claim 10, saving the context of the current thread from the register file to the context cache and sending the context of a new thread from the context cache to the register file concurrently to automatically interchange a required number of data items between the register file and the context cache, when software, such as an operating system, issuing a swap instruction for interchanging contexts, including a thread identifier as an operand, if the swap instruction is executed.

12. The context switching method according to claim 10, transferring the data of a context from the register file to the context cache and not transferring the data of a context from the context cache to the register file, when software, such as an operating system, issuing a backup instruction for saving a context, including a thread identifier as an operand, if the backup instruction is executed.

13. The context switching method according to claim 10, transferring the data of a context from the context cache to the register file and not transferring the data of a context from the register file to the context cache, when software, such as an operating system, issuing a restore instruction for restoring a context, including a thread identifier as an operand, if the restore instruction is executed.

14. A context switching program for switching a plurality of contexts on a computer by using a context switching unit comprising:

a register file having stored a context related to a thread to be executed by an arithmetic logic unit or a memory access unit, the register file comprising a read port, a write port, a context-switching read port, and a context-switching write port;

a context cache for caching a context, the context cache comprising a read port and a write port, being connected directly to the register file, and being contained in a central processing unit in a on-chip manner;

a context switching bus for connecting the register file and the context cache, the context switching bus comprising a restore bus and a save bus for connecting the read port and the write port of the context cache to the context-switching write port and the context-switching read port of the register file respectively; and

a thread control unit for controlling data transfer between the context cache and the register file, the thread control unit comprising a thread identifier table for storing a thread identifier for identifying the context of a thread stored in the context cache and being connected in parallel with the arithmetic logic unit and the memory access unit,

the context switching program permits the computer to execute;

a step in which the thread control unit receives a context switch instruction for executing a save operation and a restore operation concurrently and the identifier of a new thread to be interchanged, when a context switch which executes both a context save operation and a context restore operation in parallel occurs;

a step in which the thread control unit obtains a restore address where a new context to be interchanged is stored in the context cache and the save register identifier indicating the location where the current context is stored in the register file, by searching through the thread identifier table in accordance with the thread identifier;

a step in which the thread control unit sends the obtained address to the context cache and sends the register identifier to the register file concurrently;

a step in which the register file, in accordance with the register identifier given by the thread control unit, outputs the data of the context to be saved from the context-switching read port and, concurrently writes the data of the context to be restored, sent from the read port of the context cache to the context-switching write port through the restore bus, in the register corresponding to the register identifier;

a step in which the context cache, in accordance with the address given by the thread control unit, outputs the data of the context to be restored from the read port and, concurrently writes the data of the context to be saved sent from the context-switching read port of the register file to the write port via the save bus; and

wherein the context switching unit switches contexts by executing an operation for restoring a context from the context cache to the register file and an operation for saving a context from the register file to the context cache concurrently.

15. A computer-readable recording medium having recorded a context switching program for switching a plurality of contexts on a computer by using a context switching unit comprising:

a register file having stored a context related to a thread to be executed by an arithmetic logic unit or a memory access unit, the register file comprising a read port, a write port, a context-switching read port, and a context-switching write port;

a context cache for caching a context, the context cache comprising a read port and a write port, being connected directly to the register file, and being contained in a central processing unit in a on-chip manner;

a context switching bus for connecting the register file and the context cache, the context switching bus comprising a restore bus and a save bus for connecting the read port and the write port of the context cache to the context-switching write port and the context-switching read port of the register file respectively; and

a thread control unit for controlling data transfer between the context cache and the register file, the thread control unit comprising a thread identifier table for storing a thread identifier for identifying the context of a thread stored in the context cache and being connected in parallel with the arithmetic logic unit and the memory access unit,

the context switching program for letting the computer execute;

a step in wherein the thread control unit receives a context switch instruction for executing a save operation and a restore operation concurrently and the identifier of a new thread to be interchanged, when a context switch which executes both a context save operation and a context restore operation in parallel occurs;

a step in which the thread control unit obtains a restore address where a new context to be interchanged is stored in the context cache and the save register identifier indicating the location where the current context is stored in the register file, by searching through the thread identifier table in accordance with the thread identifier;

a step in which the thread control unit sends the obtained address to the context cache and sends the register identifier to the register file concurrently;

a step in which the register file, in accordance with the register identifier given by the thread control unit, outputs the data of the context to be saved from the context-switching read port and, concurrently writes the data of the context to be restored, sent from the read port of the context cache to the context-switching write port through the restore bus, in the register corresponding to the register identifier;

a step in which the context cache, in accordance with the address given by the thread control unit, outputs the data of the context to be restored from the read port and, concurrently writes the data of the context to be saved sent from the context-switching read port of the register file to the write port via the save bus; and

wherein the context switching unit switches contexts by executing an operation for restoring a context from the context cache to the register file and an operation for saving a context from the register file to the context cache concurrently.