CMOS image sensor and method of fabricating the same

• US 20070023764A1
• Filed: 07/24/2006
• Published: 02/01/2007
• Est. Priority Date: 07/25/2005
• Status: Active Grant

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: Kim, Hyung
• Granted Patent: US 7,573,082 B2
• Time in Patent Office: Days
• US Class Current: 257/80
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

A CMOS image sensor and a method of fabricating the same are provided. In the CMOS image sensor, a device isolation layer is formed in a substrate to define an active region, and a photodiode is formed in the active region. A floating diffusion region is formed at a position spaced apart from the photodiode, and first and second gates are overlapped with one end of the photodiode and one end of the floating diffusion region, respectively. A third gate is disposed between the first gate and the second gate and overlapped with an upper portion of the device isolation layer and a predetermined portion of the floating diffusion region. An insulating layer is formed on the resulting structure where the third gate is formed. A buried contact has a first contact and a second contact, which are sequentially stacked to pass through the insulating layer and the third gate and to connect the third gate to the floating diffusion region disposed under the third gate.

Claims

1. A CMOS image sensor comprising:

a device isolation layer formed in a substrate to define an active region;

a photodiode formed in the active region;

a floating diffusion region formed at a position spaced apart from the photodiode;

first and second gates overlapped with one end of the photodiode and one end of the floating diffusion region, respectively;

a third gate disposed between the first gate and the second gate and overlapped with an upper portion of the device isolation layer and a predetermined portion of the floating diffusion region;

an insulating layer formed on the resulting structure where the third gate is formed; and

a buried contact having a first contact and a second contact, the first contact and the second contact being sequentially stacked to pass through the insulating layer and the third gate and to connect the third gate to the floating diffusion region disposed under the third gate.

2. The CMOS image sensor according to claim 1,

wherein each of the first gate, the second gate, and the second gate has a stacked structure of a gate dielectric layer and a gate electrode.

3. The CMOS image sensor according to claim 2,

wherein the gate electrode has a multi-layer structure in which a polysilicon layer and a metal layer are sequentially stacked.

4. The CMOS image sensor according to claim 1,

wherein the first gate, the second gate, and the third gate have spacers on sidewalls thereof.

5. The CMOS image sensor according to claim 1,

wherein a diameter of the second contact is greater than or equal to that of the first contact.

6. The CMOS image sensor according to claim 1,

wherein the buried contact is formed by wholly or partially overlapping the first contact with the second contact.

7. The CMOS image sensor according to claim 6,

wherein when the first contact and the second contact are partially overlapped with each other, the first contact and the second contact are overlapped in a moving direction of electrons.

8. The CMOS image sensor according to claim 1,

wherein the substrate is formed using a semiconductor layer.

9. The CMOS image sensor according to claim 8, wherein the semiconductor layer is formed by stacking a highly doped P++ layer and a P-epi layer in sequence.

10. A method of fabricating a CMOS image sensor, comprising:

forming a device isolation layer in a substrate to define an active region;

forming a photodiode and a floating diffusion region in the active region, the photodiode and the floating diffusion region being spaced apart from each other;

forming a first gate and a second gate to overlap one end of the photodiode and one end of the floating diffusion region, and forming a third gate between the first gate and the second gate, the third gate being partially overlapped with an upper portion of the device isolation layer and a predetermined portion of the floating diffusion region;

etching a predetermined portion of the third gate to form a first contact hole exposing an upper surface of the floating diffusion region;

forming an insulating layer on the entire surface of a resulting structure where the first contact hole is formed;

etching the insulating layer disposed at a position corresponding to the first contact hole so as to form a second contact exposing an upper surface of the floating diffusion region through the first contact hole; and

filling the first contact hole and the second contact hole with metal so as to form a buried contact.

11. The method according to claim 10, further comprising:

forming spacers on sidewalls of the first gate, the second gate, and the third gate before forming the first contact hole.

12. The method according to claim 10, further comprising:

forming spacers on sidewalls of the first gate, the second gate, and the third gate after forming the first contact hole.

13. The method according to claim 10,

wherein the substrate is formed using a semiconductor layer.

14. The method according to claim 13,

wherein the semiconductor layer is formed by stacking a highly doped P++ layer and a P-epi layer in sequence.

15. The method according to claim 10, further comprising:

performing an impurity ion implantation process on the exposed floating diffusion region after forming the first contact hole.