Semiconductor devices having different gate dielectric layers and methods of manufacturing the same

• US 20070023842A1
• Filed: 05/12/2006
• Published: 02/01/2007
• Est. Priority Date: 11/12/2003
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jong-ho, Jung, Hyung-suk, Lim, Ha-jin, Kim, Yun-seok
• Application Number:
  US11/432,717
• Publication Number:
  US 20070023842A1
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02222 the compound being a silazane
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/3142 of nano-laminates, e.g. alternating layers of Al203-Hf02
• CPC Class Codes: H01L 21/31645 Deposition of Hafnium oxides, e.g. HfO2
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence

Abstract

A first transistor includes a first channel region of a first conductivity type located at a first surface region of a semiconductor substrate, a first gate dielectric which includes a first HfO₂ layer located over the first channel region, and a first gate located over the first gate dielectric. The first gate includes a first polysilicon layer doped with an impurity of the first conductivity type. The second transistor includes a second channel region of a second conductivity type located at a second surface region of the semiconductor substrate, a second gate dielectric which includes a second HfO₂ layer and an Al₂O₃ layer located over the second channel region, and a second gate located over the second gate dielectric. The second gate includes a second polysilicon layer doped with an impurity of the second conductivity type, and the second conductivity type is opposite the first conductivity type.

Claims

1. A semiconductor device comprising:

a first transistor comprising a first channel region of a first conductivity type located at a first surface region of a semiconductor substrate, a first gate dielectric which includes a first HfO₂ layer located over the first channel region, and a first gate located over the first gate dielectric, wherein the first gate includes a first polysilicon layer doped with an impurity of the first conductivity type; and

a second transistor comprising a second channel region of a second conductivity type located at a second surface region of the semiconductor substrate, a second gate dielectric which includes a second HfO₂ layer and an Al₂O₃ layer located over the second channel region, and a second gate located over the second gate dielectric, wherein the second gate includes a second polysilicon layer doped with an impurity of the second conductivity type,

wherein the second conductivity type is opposite the first conductivity type.

2. The semiconductor device of claim 1, wherein the first conductivity type is n-type, and the second conductivity type is p-type.

3. The semiconductor device of claim 2, wherein the first gate dielectric further includes a low-k interface layer located between the first HfO₂ layer and the first channel region.

4. The semiconductor device of claim 3, wherein the interface layer includes at least one of silicon oxide, silicon oxynitride or silicate.

5. The semiconductor device of claim 3, wherein a thickness of the interface layer is in a range from about 0.2 Å

to about 15 Å

.

6. The semiconductor device of claim 3, wherein a thickness of the first HfO₂ layer is in a range from about 0.2 Å

to about 50 Å

.

7. The semiconductor device of claim 2, wherein the second gate dielectric further includes a low-k interface layer located between the second HfO₂ layer and the first channel region.

8. The semiconductor device of claim 7, wherein the interface layer includes at least one of silicon oxide, silicon oxynitride or silicate.

9. The semiconductor device of claim 7, wherein a thickness of the interface layer is in a range from about 0.2 Å

to about 15 Å

.

10. The semiconductor device of claim 7, wherein each of the second HfO₂ layer and the Al₂O₃ layer has a thickness in a range-from about 0.2 Å

to about 50 Å

.

11. The semiconductor device of claim 2, further comprising at least one of a first metal nitride layer located between the first gate dielectric and the first polysilicon layer, and a second metal nitride layer located between the second gate dielectric and the second polysilicon layer.

12. The semiconductor device of claim 11, wherein each of the first metal nitride layer and the second metal nitride layer has a thickness in a range from about 0.2 Å

to about 50 Å

.

13. The semiconductor device of claim 11, wherein each of the first metal nitride layer and the second metal nitride layer includes nitrogen and at least one metal selected from the group consisting of W, Mo, Ti, Ta, Al, Hf, Zr, Si and Al.

14. The semiconductor device of claim 1, wherein a thickness of the first gate dielectric is different than a thickness of the second gate dielectric.

15. The semiconductor device of claim 2, wherein a thickness of second gate dielectric is greater than a thickness of the first gate dielectric.

16. The semiconductor device of claim 1, wherein at least one of the first HfO₂ layer, the second HfO₂ layer and the Al₂O₃ layer includes nitrogen.

17. A method of manufacturing a semiconductor device, comprising:

forming a first high-k material layer over a first MOS region and a second MOS region of a semiconductor substrate, the first MOS region having a first channel of a first conductivity type, and the second MOS region having a second channel of a second conductivity type which is opposite the first conductivity type;

annealing the first high-k material layer;

forming a second high-k material layer over the annealed first high-k material layer, wherein the second high-k material layer has a different material composition than the first high-k material layer;

annealing the second high-k material layer;

selectively removing the annealed second high-k material layer in one of the first and the second MOS regions to expose the annealed first high-k material layer in the other of the first and second MOS regions; and

forming a conductive layer over the first and second high-k material layers.

18. The method of claim 17, further comprising forming an interface layer of a low-k material on the semiconductor substrate in the first MOS region and the second MOS region before forming the first high-k material layer.

19. The method of claim 18, wherein the interface layer includes at least one of silicon oxide, silicon oxynitride layer, and silicate.

20. The method of claim 18, wherein the thickness of the interface layer is in a range from about 0.2 Å

to about 15 Å

.

21. The method of claim 17, wherein the first MOS region is an NMOS region and the second MOS region is a PMOS region, wherein the annealed second high-k material layer is removed in the NMOS region to expose the annealed first high-k material layer in the PMOS region, and wherein the first high-k material layer comprises HfO₂.

22. The method of claim 21, wherein the annealing of the first high-k material layer is performed at a temperature from about 750°

C. to 1050°

C.

23. The method of claim 21, wherein the annealing of the first high-k material layer is performed in an atmospheric gas including at least one compound selected from the group consisting of N₂, NO, N₂O, NH₃ and O₂.

24. The method of claim 21, wherein the first high-k material layer is formed to a thickness of about 0.2 Å

to about 50 Å

.

25. The method of claim 21, wherein the second high-k material layer includes Al₂O₃.

26. The method of claim 25, wherein the annealing of the second high-k material layer is performed at a temperature of about 400°

C. to about 950°

C.

27. The method of claim 25, wherein the annealing of the second high-k material layer is performed in a vacuum.

28. The method of claim 25, wherein the annealing of the second high-k material layer is performed in an atmospheric gas including at least one compound selected from the group consisting of N₂, NO, N₂O, NH₃ and O₂.

29. The method of claim 25, wherein the second high-k material layer is formed to a thickness of about 0.2 Å

to about 50 Å

.

30. The method of claim 25, wherein the selective removal of the second high-k material layer is performed in the first MOS region.

31. The method of claim 25, wherein the selective removal of the second high-k material layer comprises selectively wet etching the second high-k material layer using an etch selectivity between the annealed first high-k material layer and the annealed second high-k material layer.

32. The method of claim 25, wherein the selective removal of the second high-k material layer is performed using a cleaning solution including HF.

33. The method of claim 25, wherein the selective removal of the second high-k material layer comprises selectively removing the second high-k material layer from the NMOS region using a photoresist pattern covering the PMOS region as an etching mask, and removing the photoresist pattern using a stripper after selectively removing the second high-k material layer from the NMOS region.

34. The method of claim 25, wherein the selective removal of the second high-K material layer is performed using a cleaning solution including HF.

35. The method of claim 25, further comprising annealing a resulting structure obtained after selective removal the second high-k material layer and before forming the conductive layer.

36. The method of claim 35, wherein the annealing of the resulting structure is performed under atmospheric gas including a compound selected from the group consisting of N₂, NO, N₂O, NH₃ and O₂.

37. The method of claim 35, wherein the annealing of the resulting structure is performed at a temperature of about 750°

C. to about 1050°

C.

38. The method of claim 17, wherein the forming of the conductive layer includes:

forming a non-conductive polysilicon layer on the first high-k material layer and the second high-k material layer; and

doping the non-conductive polysilicon layer with an impurity.

39. The method of claim 38, wherein the doping of the non-conductive polysilicon layer comprises doping the non-conductive polysilicon layer with an impurity of the first conductivity type in the first MOS region, and doping the non-conductive polysilicon layer with an impurity of the second conductivity type in the second MOS region.

40. The method of claim 38, wherein the forming of the conductive layer further includes forming a metal nitride layer on the first high-k material layer and the second high-k material layer before forming the non-conductive polysilicon layer, wherein the non-conductive polysilicon layer is formed on the metal nitride layer.

41. The method of claim 40, wherein the thickness of the metal nitride layer is in a range from about 0.2 Å

to about 50 Å

.

42. The method of claim 40, wherein the metal nitride layer includes nitrogen and at least one metal selected from the group consisting of W, Mo, Ti, Ta, Al, Hf, Zr, Si and Al.