IC with on-die power-gating circuit

• US 20070023878A1
• Filed: 07/29/2005
• Published: 02/01/2007
• Est. Priority Date: 07/29/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Burton, Edward
• Granted Patent: US 7,598,630 B2
• Time in Patent Office: Days
• US Class Current: 257/675
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/0105 Tin [Sn]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1433 Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19042 being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In some embodiments a semiconductor device is described that includes, on a single die, both a functional circuit and a power-gating circuit. The power-gating circuit may be used to control the power delivered to core circuit elements on the semiconductor device. The power may be provided to and possibly from the power-gating circuit using underutilized die connection elements. Other embodiments are otherwise disclosed herein.

Claims

1. A semiconductor die, comprising:

a plurality of die connection elements;

a power-gating circuit electrically connected to a portion of said die connection elements, wherein at least one of the die connection elements is not over the power-gating circuit; and

a functional circuit electrically connected to said power-gating circuit, wherein power being provided to said functional circuit is controlled by said power-gating circuit switchably interconnecting the portion of said die connection elements to said functional circuit.

2. The die of claim 1, wherein said power-gating circuit includes one or more MOSFETs.

3. The die of claim 1, wherein said die connection elements are C4 bumps.

4. The die of claim 1, wherein said functional circuit includes a microprocessor.

5. The die of claim 1, wherein said functional circuit includes at least one cache memory array.

6. The die of claim 5, wherein at least one of the portion of said die connection elements is positioned over the cache memory array.

7. The die of claim 1, further comprising a power management circuit electrically connected to said power-gating circuit, wherein said power management circuit provides a gating signal for operating said power-gating circuit.

8. The die of claim 7, wherein said power management circuit is also electrically connected to said functional circuit.

9. The die of claim 1, wherein

said power gating circuit includes a plurality of power gating circuits;

and

said functional circuit includes a corresponding plurality of functional circuits, wherein power being provided to each of the plurality of functional circuit is independently controlled by corresponding one of the plurality of power-gating circuits.

10. The die of claim 9, wherein at least a subset of the plurality of functional circuits are microprocessors.

11. The die of claim 10, wherein power to non-active microprocessors is gated.

12. The die of claim 1, further comprising metal layers to electrically connect said power-gating circuit to the portion of said die connection elements and to said functional circuit.

13. The die of claim 12, wherein said metal layers are interdigitated over said power-gating circuit.

14. A device, comprising:

a substrate;

a power supply input;

a conductive area, on or in the substrate, electrically connected to the power supply input; and

a semiconductor die coupled to the substrate, the die including;

a functional circuit; and

a power-gating circuit, electrically connected to the conductive area and the functional circuit, to switchably provide power to the functional circuit, wherein the power-gating circuit is electrically connected to the conductive area via die connection elements, and wherein at least a portion of the die connection elements are not over the power-gating circuit.

15. The device of claim 14, wherein the power-gating circuit includes one or more MOSFETs.

16. The device of claim 14, wherein the die connection elements are C4 bumps.

17. The device of claim 14, wherein the functional circuit includes a microprocessor.

18. The device of claim 14, wherein the functional circuit includes at least one cache memory array and the at least a portion of the die connection elements are over the cache memory array.

19. The device of claim 14, wherein the conductive area includes an ungated conductive area to electrically connect the power supply input to the power-gating circuit;

and

a gated conductive area to electrically connect the power-gating circuit to the functional circuit.

20. The device of claim 19, wherein the functional circuit is electrically connected to the gated conductive area via die connection elements over the functional circuit.

21. The device of claim 19, wherein the ungated conductive area and the gated conductive area are interdigitated.

22. The device of claim 19, wherein the ungated conductive area and the gated conductive area include clusters of pads for coupling to the semiconductor die.

23. The device of claim 19, wherein the semiconductor die further includes metal layers to electrically connect said power-gating circuit to the die connection elements associated with the ungated conductive area and the gated conductive area.

24. The device of claim 14, wherein

the power gating circuit includes a plurality of power gating circuits;

and

the functional circuit includes a corresponding plurality of functional circuits, wherein power being provided to each of the plurality of functional circuit is independently controlled by corresponding one of the plurality of power-gating circuits.

25. The device of claim 14, wherein said semiconductor die includes a plurality of semiconductor die and said conductive area includes an associated plurality of conductive areas aligned with a corresponding semiconductor die.

26. A computer comprising:

an off-die memory device; and

a processor die, comprising;

a plurality of die connection elements, wherein a first subset of the plurality of die connection elements receive power;

a processor circuit;

a power-gating circuit electrically connected between the first subset of die connection elements and the processor circuit, wherein a second subset that is at least a portion of the first subset of die connection elements are not over the power-gating circuit, and wherein the power-gating circuit controls the application of power to the processor circuit by switchably interconnecting the first subset of the die connection elements to the processor circuit.

27. The computer of claim 26, wherein the processor circuit includes at least one cache memory array, and wherein a third subset that is at least a portion of the second subset of the die connection elements is positioned over the cache memory array.

28. The computer of claim 26, further comprising a substrate having

an ungated conductive area to electrically connect a power supply input to an input of the power gating circuit via the first subset of the die connection elements;

and

a gated conductive area electrically connected to an output of the power gating circuit via a fourth subset of die connection elements and to the functional circuit via a fifth subset of die connection elements that are above the functional circuit, wherein a sixth subset that is at least a portion of the fourth subset of die connection elements are not over the power-gating circuit.

29. The computer of claim 28, wherein power from the substrate is provided to and from the power gating circuit via underutilized die connection elements.

30. The computer of claim 28, wherein the fourth subset of die connection elements and the fifth set of die connection elements are connected via metal layers in the gated conductive area.