All MOS power-on-reset circuit

• US 20070024332A1
• Filed: 07/28/2005
• Published: 02/01/2007
• Est. Priority Date: 07/28/2005
• Status: Abandoned Application

• Current Assignee: Standard Microsystems Corporation (Microchip Technology Incorporated)
• Original Assignee: Standard Microsystems Corporation (Microchip Technology Incorporated)
• Inventors: McLeod, Scott
• Application Number:
  US11/192,152
• Publication Number:
  US 20070024332A1
• Time in Patent Office: Days
• US Class Current: 327/143
• CPC Class Codes: H03K 17/223 in field-effect transistor switches

Abstract

A reliable, integrated POR (power-on-reset) circuit with a compact and small area. In one set of embodiments, the POR circuit comprises NMOS and PMOS devices, where a combination of the respective threshold voltages of the NMOS and PMOS devices is used to set the POR threshold. The NMOS and PMOS devices may be coupled in a configuration resulting in a POR threshold that is a function of the PMOS threshold voltage and a scaled version of the NMOS threshold voltage. The scaling factor may be a function of the transconductance parameters of the NMOS and PMOS devices. Additional NMOS devices may be configured in the POR circuit to provide hysteresis functionality, with one of the NMOS devices coupling to one of the original NMOS devices. The scaling factor used in determining the POR threshold in case of a falling supply voltage may then be a function of the transconductance parameters of the original NMOS and PMOS devices and the additional NMOS device coupling to one of the original NMOS devices.

Claims

1. A power-on-reset (POR) circuit having a POR output, the POR circuit comprising:

first and second pairs of transistors, wherein the POR circuit is configured to be coupled to a voltage supply, wherein the voltage supply is configured to provide a supply voltage, wherein the POR circuit is operable to monitor a rise of the supply voltage, and to change a voltage state of the POR output from a POR state to a non-POR state upon the supply voltage reaching a first threshold value;

wherein the first threshold value is defined by a function of;

a first device-characteristic of respective first transistors of the first and second pairs of transistors; and

a function of a first scaling factor and the first device-characteristic of respective second transistors of the first and second pairs of transistors, wherein the first scaling factor is a function of a respective second device-characteristic of each transistor of the first and second pairs of transistors.

2. The POR circuit of claim 1, further comprising a fifth transistor coupled to the first pair of transistors, and a sixth transistor coupled to the fifth transistor, wherein the POR circuit is further operable to monitor a fall of the supply voltage, and to change the voltage state of the POR output from a non-POR state to a POR state upon the supply voltage reaching a second threshold value;

wherein the second threshold value is defined by a function of;

the first device-characteristic of the respective first transistors of the first and second pairs of transistors; and

a function of a second scaling factor and the first device-characteristic of the fifth and sixth transistors and the respective second transistors of the first and second pairs of transistors, wherein the second scaling factor is a function of the respective second device-characteristic of each transistor of the first and second pairs of transistors, and the respective second device-characteristic of the fifth transistor.

3. The POR circuit of claim 2, wherein the respective first transistors of the first and second pairs of transistors comprise PMOS devices, and the respective second transistors of the first and second pairs of transistors and the fifth and sixth transistors comprise NMOS devices.

4. The POR circuit of claim 3, wherein the first device-characteristic comprises a switching threshold voltage.

5. The POR circuit of claim 4, wherein the second device-characteristic comprises a transconductance parameter that is a function of transistor geometry and process parameters.

6. The POR circuit of claim 5, wherein the transistor geometry comprises transistor channel-width to transistor channel-length ratio.

7. The POR circuit of claim 2, wherein the POR state comprises a high voltage and the non-POR state comprises a low voltage.

8. A method for generating a POR output signal, the method comprising:

a POR circuit monitoring a rise of a supply voltage; and

the POR circuit changing a voltage state of the POR output signal from a POR state to a non-POR state upon the supply voltage reaching a first threshold value;

wherein the first threshold value is defined by a function of;

a first device-characteristic of respective first transistors of first and second pairs of transistors comprised in the POR circuit; and

a function of a first scaling factor and the first device-characteristic of respective second transistors of the first and second pairs of transistors, wherein the first scaling factor is a function of a respective second device-characteristic of each transistor of the first and second pairs of transistors.

9. The method of claim 8, further comprising:

the POR circuit monitoring a fall of the supply voltage; and

the POR circuit changing a voltage state of the POR output signal from a non-POR state to a POR state upon the supply voltage reaching a second threshold value;

wherein the second threshold value is defined by a function of;

the first device-characteristic of the respective first transistors of the first and second pairs of transistors; and

a function of a second scaling factor and the first device-characteristic of a fifth transistor coupled to the first pair of transistors and a sixth transistor coupled to the fifth transistor and the respective second transistors of the first and second pairs of transistors, wherein the second scaling factor is a function of the respective second device-characteristic of each transistor of the first and second pairs of transistors, and the respective second device-characteristic of the fifth transistor.

10. The method of claim 9, wherein the respective first transistors of the first and second pairs of transistors comprise PMOS devices, and the respective second transistors of the first and second pairs of transistors and the fifth and sixth transistors comprise NMOS devices.

11. The method of claim 10, wherein the first device-characteristic comprises a switching threshold voltage.

12. The method of claim 11, wherein the second device-characteristic comprises a transconductance parameter that is a function of transistor geometry and process parameters.

13. The POR circuit of claim 12, wherein the transistor geometry comprises transistor channel-width to transistor channel-length ratio.

14. The method of claim 9, wherein the POR state comprises a high voltage and the non-POR state comprises a low voltage.

15. A POR circuit comprising:

a first PMOS device, wherein a drain terminal of the first PMOS device is configured to couple to a gate terminal of the first PMOS device, and wherein a source terminal of the first PMOS device is configured to couple to a voltage supply (Vdd);

a first NMOS device, wherein a drain terminal of the first NMOS device is configured to couple to a drain terminal of the first PMOS device, wherein the drain terminal of the first NMOS device is configured to couple to a gate terminal of the first NMOS device, and wherein and a source terminal of the first NMOS device is configured to couple to signal ground (Vss);

a second PMOS device, wherein a gate terminal of the second PMOS device is configured to couple to Vss, and wherein a source terminal of the second PMOS device is configured to couple to Vdd; and

a second NMOS device, wherein a drain terminal of the second NMOS device is configured to couple to a drain terminal of the second PMOS device, wherein a gate terminal of the second NMOS device is configured to couple to the gate terminal of the first NMOS device, and wherein a source terminal of the second NMOS device is configured to couple to Vss;

wherein the coupled respective drain terminals of the second PMOS device and the second NMOS device comprise a first output of the POR circuit.

16. The POR circuit of claim 15, further comprising:

a third NMOS device, wherein a drain terminal of third NMOS device is configured to couple to the first output, and wherein a gate terminal of the third NMOS device is configured to couple to the gate terminal of the second NMOS device;

a fourth NMOS device, wherein a drain terminal of the fourth NMOS device is configured to couple to a source terminal of the third NMOS device, and wherein a source terminal of the fourth NMOS device is configured to couple to Vss;

a first inverter, wherein an input of the first inverter is configured to couple to the first output, and wherein an output of the first inverter is configured to couple to a gate terminal of the fourth NMOS device; and

a second inverter, wherein an input of the second inverter is configured to couple to the output of the first inverter, and wherein an output of the second inverter is configured as a second output of the POR circuit.