Active pixel sensor with mixed analog and digital signal integration

• US 20070024727A1
• Filed: 09/29/2006
• Published: 02/01/2007
• Est. Priority Date: 10/29/1998
• Status: Active Grant

• Current Assignee: Vladimir Berezin
• Original Assignee: Vladimir Berezin
• Inventors: Berezin, Vladimir
• Granted Patent: US 7,956,912 B2
• Time in Patent Office: Days
• US Class Current: 348/308
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/587 acquired sequentially, e.g. using the combination of odd and even image fields
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

An active pixel sensor includes mixed analog and digital signal integration on the same substrate. The analog part of the array forms the active pixel sensor, and the digital part of the array does digital integration of the signal.

Claims

1-8. -8. (canceled)

9. A processing system comprising:

an array of pixels disposed on a substrate;

a first analog signal processor for processing a plurality of analog signals received from a first pixel in the array of image sensor pixels during an integration period of said pixel;

a first circuit for converting said processed analog signals to digital signals;

a first digital signal processor for receiving and processing said digital signals; and

a first digital memory array for storing said digital signals,

wherein said digital signals are accumulated by said processing system, the accumulation of which represents a digital integrated value for the integration period of the first pixel.

10. The processing system of claim 9, wherein the circuit for converting said processed analog signals is an oversampling converter.

11. The processing system of claim 9, wherein said analog signal processor comprises a column analog double sampling circuitry.

12. The processing system of claim 11, wherein said column analog double sampling circuitry comprises a sample circuit for a pixel signal and a sample circuit for a reference signal from said pixel to decrease fixed pattern noise.

16. The processing system of claim 9, wherein said image sensor array is a CMOS active pixel sensor array.

17. The processing system of claim 9, wherein said first pixel is sufficiently small so that it lacks sufficient capacity to integrate incoming photons for the entirety of said integration period.

18. The processing system of claim 9, wherein said first analog signal processor comprises at least one preamplifier with adjustable gain.

19. A method of operating an imager comprising:

capturing an image with a pixel sensor array during an integration period;

causing pixels in the array to each produce electrical signals representing said image;

sampling said electronic signals for each pixel multiple times during said integration period;

converting said electrical signals for each pixel to digital signals;

accumulating and storing said digital signals for each pixel, said accumulated digital signals for each pixel representing a digital integrated signal for said integration period.

20. The method of claim 19, further comprising outputting said integrated signal for each pixel.

21. The method of claim 19, wherein said digital signals for each pixel comprise at least one of each of a light intensity signal and a reference signal.

22. The method of claim 19, wherein at least a first set of said electrical signals is accumulated and stored in a first memory array and at least a second set of electrical signals is accumulated and stored in a second memory array.

23. The method of claim 22, wherein the act of converting said first set of electrical signals is performed by a first analog to digital converter and the act of converting said second set of electrical signals is performed by a second analog to digital converter.

24. The method of claim 23, further comprising outputting at least one integrated signal from each of said first and second digital memory arrays.

25. An imager circuit comprising:

an active pixel image sensor array;

at least one circuit for sampling and converting analog information from a plurality of pixels in said array to digital values;

at least one digital memory array for storing and accumulating said digital values, wherein said plurality of pixels in said active pixel image sensor array are sampled multiple times during an integration period and each sampled value is stored and accumulated in a digital memory array, said accumulated values representing a respective integrated signal for each pixel during said integration period; and

a controller for controlling the sampling of analog information from said pixels and said storage of digital values in said at least one digital memory array.

26. The imager circuit of claim 25, further comprising at least one analog signal processor electrically connected to receive said analog information from said image sensor array and to provide said information to said at least one analog to digital converter.

27. The imager circuit of claim 26, wherein said at least one analog signal processor comprises at least one preamplifier with adjustable gain.

28. The imager circuit of claim 26, wherein said at least one analog signal processor comprises column analog double sampling circuitry.

29. The imager circuit of claim 25, wherein said at least one digital memory array comprises first and second digital memory arrays.

30. The imager circuit of claim 29, wherein said first and second digital memory arrays are respectively located on first and second opposite sides of said image sensor array.

31. The imager circuit of claim 29, further comprising first and second digital signal processors for providing respective first and second sets of digital values to said first and second digital memory arrays.