Scalable subsystem architecture having integrated cooling channels

• US 20070025079A1
• Filed: 07/27/2006
• Published: 02/01/2007
• Est. Priority Date: 08/01/2005
• Status: Active Grant

• Current Assignee: Salmon Technologies LLC
• Original Assignee: Salmon Technologies LLC
• Inventors: Salmon, Peter
• Granted Patent: US 7,586,747 B2
• Time in Patent Office: Days
• US Class Current: 361/688
• CPC Class Codes: G02B 6/43 Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 23/142 Metallic substrates having insulating layers
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/467 by flowing gases, e.g. air H01L23/473 takes precedence
• CPC Class Codes: H01L 23/473 by flowing liquids H01L23/4332, H01L23/4338 take precedence
• CPC Class Codes: H01L 23/498 Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers shape of the substrate H01L23/13
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1627 : stacked type assemblies, e.g. stacked multi-cavities
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: Y10T 29/49128 : Assembling formed circuit to base

Abstract

A method for building scalable electronic subsystems is described. Stackable modules employ copper substrates with solder connections between modules, and a ball grid array interface is provided at the bottom of the stack. A cooling channel is optionally provided between each pair of modules. Each module is re-workable because all integrated circuit attachments within the module employ re-workable flip chip connectors. Also, defective modules can be removed from the stack by directing hot inert gas at externally accessible solder connections.

Claims

1. A scalable electronic subsystem comprising:

a stackable module;

cooling channels provided between selected ones of said modules; and

,

coolant flowing in each of said channels.

2. The scalable subsystem of claim 1 wherein said stackable modules connect to each other using solder connections.

3. The scalable subsystem of claim 1 and including a ball grid array interface to said subsystem.

4. The scalable subsystem of claim 1 and including an interface to said subsystem employing pillar in well connectors.

5. The scalable subsystem of claim 1 wherein selected ones of said modules include a connection to an optical fiber for high bandwidth communications.

6. The scalable subsystem of claim 1 wherein said stackable module includes a copper substrate.

7. The scalable subsystem of claim 5 wherein said copper substrate includes glass-sealed copper feedthroughs.

8. The scalable subsystem of claim 5 wherein interconnection circuits are fabricated on said copper substrate.

9. The scalable subsystem of claim 1 wherein said modules include direct chip attachments employing flip chip connectors, and each of said connectors includes a conductive bump or pillar inserted into a well filled with conductive material.

10. The scalable subsystem of claim 9 wherein said conductive material is a conductive powder.

11. The scalable subsystem of claim 10 wherein said conductive powder comprises particles of alloy 80Au20Sn.

12. The scalable subsystem of claim 9 wherein said conductive material is a solder.

13. The scalable subsystem of claim 9 wherein said bumps or pillars have a height to width ratio of 2.5-10, providing a mechanically compliant interface.

14. A method for building a scalable electronic system or subsystem comprising the steps of:

a) fabricating a stackable module;

b) stacking a plurality of said modules to form said system or subsystem with a cooling channel provided between each pair of modules; and

,

c) circulating a coolant in said cooling channel.

15. The method of claim 14 wherein said stackable module is fabricated on a copper substrate.

16. The method of claim 15 and including the step of testing each of said stackable modules prior to said stacking.

17. The method of claim 16 and further including the step of re-working any defective chips in each of said tested modules prior to said stacking.

18. A re-workable and well-cooled electronic subsystem comprising:

integrated circuit chips attached to stackable modules using re-workable flip chip connectors;

spacers providing electrical feed throughs and a sealed cooling channel between each of said stackable modules;

coolant flowing in said cooling channels; and

,

solder connections between said modules and said spacers in said stack that are accessible to directed jets of hot inert gas for melting said solder in selected ones of said connections for performing said rework of said subsystem.

19. The re-workable subsystem of claim 18 wherein said integrated circuit chips include a plurality of circuit types selected from digital, analog, RF, optical, electro-optical, and integrated passives.

20. The re-workable subsystem of claim 18 wherein said stackable modules are hermetic.