Memory array with a delayed wordline boost

• US 20070025169A1
• Filed: 07/28/2005
• Published: 02/01/2007
• Est. Priority Date: 07/28/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Houston, Theodore
• Granted Patent: US 7,289,354 B2
• Time in Patent Office: Days
• US Class Current: 365/206
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

Methods and a circuit for writing to an SRAM memory cell of an array are discussed that provide improved static noise margin, and minimal risk of data upsets during write operations. The write method first rapidly raises the wordline to a lower read voltage level for access, then after a time delay that allows the cells in the selected row to establish a stabilizing differential voltage on the associated bitlines, raises the wordline voltage to a boosted or higher write voltage level. An SRAM bitline enhancement circuit may also be utilized in association with the SRAM memory array and writing method, for enhancing the differential voltage produced by an SRAM memory cell of the array on associated first and second bitlines of the array of conventional SRAM cells (e.g., a conventional 6T differential cell). In one implementation, the SRAM bitline enhancement circuit comprises a half-latch or a sense amplifier connected to associated bitline pairs of the array for amplifying the differential voltage.

Claims

1. A method of operating an SRAM memory cell of an array, the SRAM cell comprising cross-coupled amplifiers having internal pull-up transistors connected to a supply line, the method comprising:

accessing a wordline associated with the SRAM memory cell by asserting a read wordline voltage to the accessed wordline, thereby generating a bit line difference; and

asserting a write wordline voltage after generation of the bit line difference to the accessed wordline of the memory cell during a write operation.

2. The method of claim 1, wherein the write wordline voltage is asserted by ramping the voltage from the read wordline voltage to the write wordline voltage.

3. The method of claim 1, wherein the write wordline voltage is asserted by utilizing one or more intermediate voltage steps between the read wordline voltage and the write wordline voltage.

4. The method of claim 1, wherein the read wordline voltage is used during read and write operations of the memory cell, and the write wordline voltage is used during write operations.

5. The method of claim 1, wherein the read wordline voltage is about the level of the supply voltage of the array, and the write wordline voltage is boosted above the supply voltage.

6. The method of claim 1, wherein the write wordline voltage is about the level of the supply voltage of the array, and the read wordline voltage is below the level of the supply voltage.

7. The method of claim 1, further comprising delaying for a period of time after accessing the wordline, until a differential voltage is established on associated bitline pairs of the array along the accessed wordline.

8. The method of claim 7, wherein the time delay period is about the same as the read sense delay used during read sensing operations before the read sense amplifier is enabled.

9. The method of claim 7, wherein the time delay period is nearly zero, and wherein the write wordline voltage is asserted by ramping the voltage from the read wordline voltage to the write wordline voltage, thereby achieving the differential voltage on the bitlines as the wordline voltage slowly increases.

10. The method of claim 1, further comprising

selecting one of the read or write wordline voltages to be eliminated during write operations, based on predetermined fabrication process, bias condition, and operating temperature criteria.

11. The method of claim 1, further comprising

enhancing the differential voltage produced by the selected memory cell on associated first and second bitlines of the array before the write wordline voltage is asserted to the wordline using an SRAM bitline enhancement circuit.

12. An integrated circuit comprising:

an array of SRAM memory cells arranged in rows and columns, the SRAM cell comprising cross-coupled amplifiers having internal pull-up transistors connected to a supply line;

a plurality of wordlines associated with the rows of cells of the array;

a plurality of bit lines associated with the columns of cells of the array;

a word line driver operable to drive a selected word line of the array, wherein the wordline driver is further operable to;

access the selected wordline associated with the SRAM memory cell by asserting a read wordline voltage to the accessed wordline, thereby generating a bit line difference; and

assert a write wordline voltage after generation of the bit line difference to the accessed wordline of the memory cell during a write operation;

wherein the voltage imposed on the bit line by an accessed cell increases the stability of the cell prior to the word line being driven to the full access voltage.

13. The circuit of claim 12, further comprising an SRAM bitline enhancement circuit for an SRAM memory array, for enhancing the differential voltage produced by an SRAM memory cell of the array on associated first and second bitlines of the array, the SRAM memory cell comprising first and second cross-coupled inverters connected to first and second latch nodes, respectively, and first and second pass transistors connected between the first and second latch nodes and the respective first and second bitlines of the array, the SRAM bitline enhancement circuit comprising:

first and second cross-coupled pull-ups connected between a supply node and first and second bitlines, respectively;

wherein an output of the first pull-up is connected to the first bitline, and an output of the second pull-up is connected to the second bitline; and

wherein an input of the first pull-up is connected to the second bitline and an input of the second pull-up is connected to the first bitline.

14. The circuit of claim 12, wherein the write wordline voltage is asserted by utilizing one or more intermediate voltage steps between the read wordline voltage and the write wordline voltage.

15. The circuit of claim 12, wherein the write wordline voltage is asserted by ramping the voltage from the read wordline voltage to the write wordline voltage.

16. The circuit of claim 12, wherein the write wordline voltage is greater than the read wordline voltage.

17. The method of claim 12, further comprising delaying for a period of time after accessing the wordline, until a differential voltage is established on associated bitline pairs of the array along the accessed wordline.

18. A method of writing to an SRAM memory cell of an array using an SRAM bitline enhancement circuit for enhancing the differential voltage produced by the memory cell on associated first and second bitlines of the array, the SRAM memory cell comprising first and second cross-coupled inverters connected to first and second latch nodes, respectively, and first and second pass transistors connected between the first and second latch nodes and the respective first and second bitlines of the array, the SRAM bitline enhancement circuit comprising first and second cross-coupled pull-ups connected between a supply node and the first and second bitlines, respectively, wherein an output of the first pull-up is connected to the first bitline, and an output of the second pull-up is connected to the second bitline, and wherein an input of the first pull-up is connected to the second bitline and an input of the second pull-up is connected to the first bitline, the method comprising:

accessing a wordline associated with the SRAM memory cell by asserting a read wordline voltage to the accessed wordline, thereby generating a bit line difference;

enhancing the differential voltage on the first and second bitlines of the array using the SRAM bitline enhancement circuit; and

asserting a write wordline voltage after generation of the bit line difference to the accessed wordline of the memory cell during a write operation after enhancing the differential voltage on the first and second bitlines.

19. The method of claim 18, wherein the bitline enhancement is accomplished about the same time that the write wordline voltage is asserted to the wordline.

20. The method of claim 18, wherein the write wordline voltage is asserted by utilizing one or more intermediate voltage steps between the read wordline voltage and the write wordline voltage.

21. The method of claim 18, further comprising delaying for a period of time after accessing the wordline, until a differential voltage is established on associated bitline pairs of the array along the accessed wordline.

22. The method of claim 21, wherein the time delay period is about the same as the read sense delay used during read sensing operations before the read sense amplifier is enabled.

23. The method of claim 21, wherein the time delay period is nearly zero, and wherein the write wordline voltage is asserted by ramping the voltage from the read wordline voltage to the write wordline voltage, thereby achieving the differential voltage on the bitlines as the wordline voltage slowly increases.

24. A method of operating a word line voltage of an SRAM cell, the method comprising:

controlling an increase and a timing of the increase of the word line voltage applied to a word line of an accessed SRAM cell, to allow the accessed cell time to establish a voltage on an associated bit line prior to the word line reaching a full word line voltage, wherein the voltage that is established on the bit line increases the stability of the cell as the word line voltage approaches the full word line voltage.

25. The method of claim 24, wherein the controlling of the word line voltage comprises increasing from a non-accessed state of the word line to a first voltage level, then after a time delay, increasing to a second voltage level, wherein the second voltage level is greater than the first voltage level of the word line.

26. The method of claim 24, wherein the controlling of the word line voltage increase and timing comprises increasing from a non-accessed state of the word line to a first voltage level, then increasing to a second voltage level, wherein the second voltage level is greater than the first voltage level of the word line.

27. The method of claim 25, wherein the word line voltage increase between the first voltage level and the second voltage level comprises one or more intermediate voltage steps.

28. The method of claim 25, wherein the word line voltage increase between the first voltage level and the second voltage level comprises ramping the voltage from the first voltage level to the second voltage level.

29. The method of claim 27, wherein the word line voltage increase to one or more of the first and second voltage levels comprises a ramped increase.

30. The method of claim 24, wherein the SRAM cell comprises a differential SRAM cell, and wherein the word line voltage on the wordline is controlled such that the cell establishes a differential voltage on an associated pair of bit lines.

31. The method of claim 30, further comprising an SRAM bitline enhancement circuit for enhancing the differential voltage established on the bit line pair.

32. The method of claim 31, wherein the SRAM bitline enhancement circuit comprises a sense amplifier used at each bitline pair.

33. The method of claim 31, wherein the SRAM bitline enhancement circuit comprises a half-latch.