GPS front end with universal digital interface

• US 20070025479A1
• Filed: 07/29/2005
• Published: 02/01/2007
• Est. Priority Date: 07/29/2005
• Status: Active Grant

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: SIRF Technology Incorporated (Qualcomm, Inc.)
• Inventors: Babitch, Daniel, Anderson, Erik, Hashemi, Majid
• Granted Patent: US 7,664,206 B2
• Time in Patent Office: Days
• US Class Current: 375/345
• CPC Class Codes: G01S 19/37 Hardware or software details of the signal processing chain
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes
• CPC Class Codes: H04L 2027/0053 Closed loops

Abstract

A radio frequency integrated circuit for a global positioning system (GPS) application mixes radio frequency GPS signals from an external source with a predetermined intermediate frequency that is less than 4 f_o. In one embodiment, the intermediate frequency is selected to be 1.5 f_o. An intermediate frequency filter then band-limits the intermediate frequency GPS signals, rolling off at a frequency in the vicinity of 2.5 MHz to achieve substantial attenuation at 3.5-4.0 MHz. An automatic gain control circuit amplifies the filtered intermediate frequency GPS signals to proper voltage levels. The amplified intermediate frequency GPS signals is then digitized by an analog-to-digital converter at a predetermined sampling rate more than twice the intermediate frequency to provide samples of a predetermined number of bits, which are then provided for base band processing by a general purpose microprocessor over an industry-standard serial bus.

Claims

1. A radio frequency integrated circuit for a global positioning system (GPS) application, comprising:

an interface for receiving radio frequency GPS signals from an external source;

a mixer which down-converts the GPS signals to a predetermined intermediate frequency that is less than 16 f_o;

an intermediate frequency filter which receives and filters the intermediate frequency GPS signals;

an automatic gain control circuit which amplifies the filtered intermediate frequency GPS signals;

an analog-to-digital converter which digitizes the amplified, filtered intermediate frequency GPS signals at a predetermined sampling rate to provide samples of a predetermined number of bits; and

an interface which provides the samples to a base band processor over an industry-standard serial bus.

2. A radio frequency integrated circuit as in claim 1, further comprising a calibration circuit for setting the pass band of the intermediate frequency filter.

3. A radio frequency integrated circuit as in claim 1, wherein the mixer comprises an image reject mixer.

4. A radio frequency integrated circuit as in claim 1, wherein a product of the predetermined sampling rate and the predetermined number of bits is less than or equal to the data rate of the industry-standard serial bus.

5. A radio frequency integrated circuit as in claim 1, wherein the predetermined intermediate frequency is substantially 1.5 f_o.

6. A radio frequency integrated circuit as in claim 5, wherein the predetermined sampling rate is substantially 6 f_o.

7. A radio frequency integrated circuit as in claim 5, wherein the predetermined frequency filter rolls off in the vicinity of 2.5 MHz.

8. A radio frequency integrated circuit as in claim 6, wherein the power spectra of the intermediate frequency filter and the analog-to-digital filter are substantially attenuated at frequencies greater than or equal to 3.5 MHz.

9. A radio frequency integrated circuit as in claim 1, wherein the industry-standard serial bus comprises a synchronous peripheral bus.

10. A radio frequency integrated circuit as in claim 1, wherein the industry-standard serial bus comprises Multi-channel Buffered Serial Port.

11. A radio frequency integrated circuit as in claim 1, wherein the radio frequency integrated circuit comprises an ON state, a STANDBY state and an OFF state.

12. A radio frequency integrated circuit as in claim 1, wherein the baseband processor comprises a general purpose microprocessor.

13. A radio frequency integrated circuit as in claim 1, wherein the baseband processor comprises an industry standard digital signal processor.

14. A radio frequency integrated circuit as in claim 1, wherein the radio frequency integrated circuit is configurable over the industry-standard serial bus.

28. A method as in claim 1, further comprising configuring the radio frequency integrated circuit over the industry-standard serial bus.

15. A method for interfacing a radio frequency integrated circuit for a global positioning system (GPS) application with a general purpose microprocessor, comprising:

receiving radio frequency GPS signals from an external source;

down-converting the GPS signals to a predetermined intermediate frequency that is less than 16 f_o;

filtering the intermediate frequency GPS signals;

providing an automatic gain control circuit which amplifies the filtered intermediate frequency GPS signals;

digitizing the anplified, filtered intermediate frequency GPS signals at a predetermined sampling rate to provide samples of a predetermined number of bits; and

providing the samples to a baseband processor over the industry-standard serial bus.

16. A method as in claim 15, further comprising calibrating the pass band of the intermediate frequency filter.

17. A method as in claim 15, wherein the mixer comprises an image reject mixer.

18. A method as in claim 15, wherein a product of the predetermined sampling rate and the predetermined number of bits is less than or equal to the data rate of the industry-standard serial bus.

19. A method as in claim 15, wherein the predetermined intermediate frequency is substantially 1.5 f_o.

20. A method as in claim 19, wherein the predetermined sampling rate is substantially 6 f_o.

21. A method as in claim 19, wherein the predetermined frequency filter rolls off in the vicinity of 2.5 MHz.

22. A method as in claim 19, wherein the power spectra of the intermediate frequency filter and the analog-to-digital filter are substantially attenuated at frequencies greater than or equal to 3.5 MHz.

23. A method as in claim 15, wherein the industry-standard serial bus comprises a synchronous peripheral bus.

24. A method as in claim 15, wherein the industry-standard serial bus comprises Multi-channel Buffered Serial Port.

25. A method as in claim 15, wherein the radio frequency integrated circuit comprises an ON state, a STANDBY state and an OFF state.

26. A method as in claim 15, wherein the baseband processor comprises a general purpose microprocessor.

27. A method as in claim 15, wherein the baseband processor comprises an industry standard digital signal processor.