Method of manufacturing a semiconductor device

• US 20070026651A1
• Filed: 07/05/2006
• Published: 02/01/2007
• Est. Priority Date: 07/05/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: You, Young-Sub, Lee, Woong, Lee, Sang-Hoon, Jee, Jung-Geun, Leam, Hun-Hyeoung, Jang, Won-Jun, Park, Jung-Hyun, Lee, Hyeon-Deok, Lee, Sang-Kyoung
• Granted Patent: US 7,410,869 B2
• Time in Patent Office: Days
• US Class Current: 438/552
• CPC Class Codes: H01L 21/32115 Planarisation
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

In a method of manufacturing a semiconductor device such as a flash memory device, an insulating pattern having an opening is formed to partially expose a surface of a substrate. A first silicon layer is formed on the exposed surface portion of the substrate and the insulating pattern. The first silicon layer has an opened seam overlying the previously exposed portion of the substrate. A heat treatment on the substrate is performed at a temperature sufficient to induce silicon migration so as to cause the opened seam to be closed via the silicon migration. A second silicon layer is then formed on the first silicon layer. Thus, surface profile of a floating gate electrode obtained from the first and second silicon layers may be improved.

Claims

1. A method of manufacturing an inchoate semiconductor device, the method comprising:

forming an insulating pattern having an opening partially exposing a surface of a substrate;

forming a first silicon layer, on the insulating pattern and the exposed surface portion of the substrate, having an opened seam overlying the previously exposed portion of the substrate;

heat treating the first silicon layer at a temperature sufficient to induce silicon migration so as to cause the opened seam to be closed; and

forming a second silicon layer on the first silicon layer after having closed the opened seam.

2. The method of claim 1, further comprising forming a silicon oxide layer on the first silicon layer before the heat treatment.

3. The method of claim 2, wherein the heat treatment is performed under an atmosphere including hydrogen, and the silicon migration is promoted by reduction reaction between hydrogen and the silicon oxide layer.

4. The method of claim 2, wherein the silicon oxide layer is formed by exposing the first silicon layer to an atmosphere including oxygen.

5. The method of claim 1, wherein a ratio of a thickness of the first silicon layer to a width of the opening is from about 0.3 to about 0.4.

6. The method of claim 1, wherein the heat treatment is performed at a temperature of about 850 to about 1000°

C.

7. The method of claim 1, wherein the first silicon layer includes impurity doped amorphous silicon and is crystallized by the heat treatment.

8. The method of claim 1, wherein the second silicon layer includes impurity doped polysilicon.

9. The method of claim 1, further comprising forming a tunnel insulating layer on the exposed surface portion of the substrate after forming the insulating pattern.

10. The method of claim 1, further comprising performing a planarization process until the Insulating pattern is exposed such that a remainder of the first silicon layer represents a floating gate pattern in the opening.

11. A method of manufacturing a semiconductor device, the method comprising:

forming a mask pattern having a first opening partially exposing a surface of a substrate;

forming a trench in the substrate using the mask pattern;

forming an insulating pattern in the first opening and the trench;

removing the mask pattern to form a second opening exposing an inchoate active region of the substrate;

forming a first silicon layer, on the exposed active region and the insulating pattern, having an opened seam overlying the inchoate active region;

heat treating the first silicon layer at a temperature sufficient to induce silicon migration so as to cause the opened seam to be closed via the silicon migration;

forming a second silicon layer on the first silicon layer after having closed the opened seam; and

performing a planarization process until the insulating pattern is exposed such that a remainder of the first silicon layer represents a floating gate pattern in the second opening.

12. The method of claim 11, further comprising forming a silicon oxide layer on the first silicon layer before the heat treatment.

13. The method of claim 12, wherein the heat treatment is performed under an atmosphere including hydrogen, and the silicon migration is promoted by reduction reaction between hydrogen and the silicon oxide layer.

14. The method of claim 12, wherein the silicon oxide layer is formed by exposing the first silicon layer to an atmosphere including oxygen.

15. The method of claim 11, wherein a ratio of a thickness of the first silicon layer to a width of the second opening is from about 0.3 to about 0.4.

16. The method of claim 11, wherein the heat treatment is performed at a temperature of about 850 to about 1000°

C.

17. The method of claim 11, wherein the first silicon layer includes impurity doped amorphous silicon and is crystallized by the heat treatment.

18. The method of claim 11, wherein the second silicon layer includes impurity doped polysilicon.

19. The method of claim 11, further comprising forming a tunnel insulating layer on the exposed active region of the substrate after removing the mask pattern.

20. The method of claim 19, further comprising:

sequentially forming a dielectric layer and a control gate conductive layer on the floating gate pattern and insulating pattern; and

sequentially patterning the control gate conductive layer, the dielectric layer, the floating gate pattern and the tunnel insulating layer so as to form a gate structure including a tunnel insulating layer pattern, a floating gate electrode, a dielectric layer pattern and a control gate electrode.

21. A method of manufacturing an inchoate semiconductor device, the method comprising:

forming an insulating pattern having an opening partially exposing a surface of a substrate;

forming a first silicon layer, on the insulating pattern and the exposed surface portion of the substrate, having an opened seam overlying the previously exposed portion of the substrate;

closing the opened seam in the first silicon layer; and

forming, after the step of closing, a second silicon layer on the first silicon layer.

22. The method of claim 21, wherein the step of closing includes inducing silicon migration which fills the opened seam.

23. The method of claim 22, wherein the step of inducing includes heat treating the first silicon layer.