Fast switching, dual frequency phase locked loop

• US 20070026814A1
• Filed: 07/26/2005
• Published: 02/01/2007
• Est. Priority Date: 07/26/2005
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Gierkink, Sander
• Granted Patent: US 7,630,698 B2
• Time in Patent Office: Days
• US Class Current: 455/73
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A fast switching, dual frequency phase locked loop comprising dual phase/frequency detectors, dual charge pumps, a pair of loop filters, and a low leakage voltage controlled oscillator. Each phase/frequency detector and associated tuning ports of the voltage controlled oscillator can be activated and deactivated separately without disturbing the charge on the loop filters.

Claims

1. A phase locked loop comprising:

a first phase/frequency detector and a second phase/frequency detector, each having two inputs and one output;

a first charge pump coupled to the output of the first phase/frequency detector;

a second charge pump coupled to the output of the second phase/frequency detector;

a first loop filter coupled to an output of the first charge pump and coupled to a first tuning port of a voltage controlled oscillator;

a second loop filter coupled to an output of the second charge pump and coupled to a second tuning port of a voltage controlled oscillator; and

the voltage controlled oscillator having an output that is coupled to the first and second phase/frequency detectors, and having first and second tuning ports with low leakage.

2. The phase locked loop of claim 1 further comprising control circuitry for activating one of the first phase/frequency detector or second phase/frequency detectors and a corresponding tuning port of the voltage controlled oscillator.

3. The phase locked loop of claim 1 wherein the voltage controlled oscillator further comprises:

a first varactor having a gate-side coupled to the first tuning port and a well-side coupled to at least one first inductor; and

a second varactor having a gate-side coupled to the second tuning port and a well-side coupled to at least one second inductor.

4. The phase locked loop of claim 3 further comprising;

a third varactor connected between the first tuning port and the well-side of the second varactor; and

a fourth varactor connected between the second tuning port and the well-side of the first varactor.

5. The phase locked loop of claim 2 wherein the control circuitry selects an output frequency for the voltage controlled oscillator.

6. The phase locked loop of claim 3 wherein the first and second varactors are accumulation-depletion varactors.

7. The phase locked loop of claim 3 wherein the first tuning port is activated by applying a bias voltage to the well-side of the first varactor;

and the second tuning port is activated by applying a bias voltage to the well-side of the second varactor.

8. A transceiver comprising:

receiver circuitry;

transmitter circuitry;

a phase locked loop coupled to the receiver circuitry and the transmitter circuitry to switchably supply at least two frequencies to enable the receiver circuitry and transmitter circuitry to operate either with a zero intermediate frequency and/or a low intermediate frequency.

9. The transceiver of claim 8 wherein the phase locked loop switches between two frequencies in about 6 uS.

10. The transceiver of claim 8 wherein the receiver and transmitter circuitry can operate in multiple modes that support various IEEE 802.11 protocols.

11. The transceiver of claim 8 wherein the transmitter circuitry operates with a zero intermediate frequency and the receiver circuitry operates either with zero intermediate frequency or low intermediate frequency.

12. The transceiver of claim 11 wherein the receiver and transmitter circuitry uses zero intermediate frequency to support an IEEE 802.11b protocol, and to support an IEEE 802.11a/g protocols, the transmitter circuitry uses zero intermediate frequency and the receiver circuitry uses low intermediate frequency.

13. A method of operating a phase locked loop comprising:

activating a first phase/frequency detector and a first tuning port of a voltage controlled oscillator, while simultaneously deactivating a second phase/frequency detector and a second tuning port of the voltage controlled oscillator, where a charge accumulated in a loop filter coupled between the second phase/frequency detector and the second tuning port does not discharge while the tuning port is deactivated.

14. The method of claim 13 wherein the second tuning port is deactivated by applying a predefined step in voltage across gate-well connections of a varactor.