Systems and methods of RF power transmission, modulation, and amplification, including Multiple Input Single Output (MISO) amplifiers

• US 20070026821A1
• Filed: 08/23/2006
• Published: 02/01/2007
• Est. Priority Date: 10/22/2004
• Status: Active Grant

• Current Assignee: ParkerVision, Inc.
• Original Assignee: ParkerVision, Inc.
• Inventors: Sorrells, David, Rawlins, Michael, Rawlins, Gregory
• Granted Patent: US 7,835,709 B2
• Time in Patent Office: Days
• US Class Current: 455/118
• CPC Class Codes: H03C 5/00 Amplitude modulation and angle modulation produced simultaneously or at will by the same modulating signal H03C7/00 takes precedence
• CPC Class Codes: H03F 1/02 Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/0233 by using a signal derived from the output signal, e.g. bootstrapping the voltage supply
• CPC Class Codes: H03F 1/0294 using vector summing of two or more constant amplitude phase-modulated signals
• CPC Class Codes: H03F 1/32 Modifications of amplifiers to reduce non-linear distortion by negative feedback H03F1/34
• CPC Class Codes: H03F 1/3205 in field-effect transistor amplifiers
• CPC Class Codes: H03F 1/3223 using feed-forward H03F1/3211 takes precedence
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2201/3215 To increase the output power or efficiency
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/45071 with semiconductor devices only
• CPC Class Codes: H03G 3/3042 in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04
• CPC Class Codes: H04B 1/04 Circuits
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence
• CPC Class Codes: H04B 1/0483 : Transmitters with multiple parallel paths
• CPC Class Codes: H04B 2001/045 : with means for improving efficiency
• CPC Class Codes: H04B 2001/0491 : with frequency synthesizers, frequency converters or modulators
• CPC Class Codes: H04L 27/20 : Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/36 : Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/362 : Modulation using more than one carrier, e.g. with quadrature carriers, separately amplitude modulated H04L27/366 takes precedence

Abstract

Methods and systems for vector combining power amplification are disclosed herein. In one embodiment, a plurality of signals are individually amplified, then summed to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one or more of the signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time-varying complex envelope signal. In another embodiment, a time-varying complex envelope signal is decomposed into a plurality of constant envelope constituent signals. The constituent signals are amplified equally or substantially equally, and then summed to construct an amplified version of the original time-varying envelope signal. Embodiments also perform frequency up-conversion.

Claims

1-24. -24. (canceled)

25. A multiple input single output (MISO) amplifier, comprising:

a plurality of inputs that receive a plurality of input signals;

a plurality of circuit branches coupled to said inputs, said circuit branches each comprising one or more transistors; and

an output;

wherein said input signals are simultaneously amplified and combined to create an output signal of said MISO amplifier.

26. The MISO amplifier of claim 25, further comprising:

biasing control circuitry.

27. The MISO amplifier of claim 26, wherein said biasing control circuitry comprises:

means for controlling one or more of output power efficiency, output linearity, and amplification stage protection.

28. The MISO amplifier of claim 25, further comprising:

means for harmonically shaping said output signal.

29. The MISO amplifier of claim 28, wherein said means for harmonically shaping said output signal comprises:

means for wave-shaping said input signals.

30. The MISO amplifier of claim 28, wherein said means for harmonically shaping said output signal comprises:

means for wave-shaping said output signal.

31. The MISO amplifier of claim 25, further comprising:

means for output stage protection.

32. The MISO amplifier of claim 31, wherein said means for output stage protection comprises:

means for limiting current through said circuit branches.

33. The MISO amplifier of claim 25, further comprising:

means for dynamically controlling said transistors of said circuit branches to thereby transition operation of said transistors along an operational range that includes switching amplifier operation and current source amplifier operation.

34. The MISO amplifier of claim 25, further comprising:

means for controlling an input differential phase and a bias of said transistors based on requirements of said output signal.

35. The MISO amplifier of claim 25, wherein output voltages of said transistors in said circuit branches are substantially equal to an output voltage of said MISO amplifier for all operational instances of time of said MISO amplifier.

36. The MISO amplifier of claim 25, wherein said circuit branches each comprises one or more power amplification sub-stages.

37. The MISO amplifier of claim 36, wherein said power amplification sub-stages each comprises at least one of a pre-driver and a driver.

38. The MISO amplifier of claim 36, further comprising one or more pull-up impedances at an output of each of said power amplifier sub-stages for biasing of said each of said power amplifier sub-stages.

39. The MISO amplifier of claim 36, further comprising matching impedances at an output of each of said power amplifier sub-stages for enhancing power transfer from said each of said power amplifier sub-stages.

40. The MISO amplifier of claim 25, further comprising one or more non- linear amplifiers.

41. The MISO amplifier of claim 25, wherein said input signals are simultaneously amplified and combined at a circuit node formed by coupling outputs of said transistors in said circuit branches, wherein said outputs of said transistors in said circuit branches are coupled together at said circuit node with a conducting wire.

42. The MISO amplifier of claim 25, wherein said input signals are simultaneously amplified and combined at a circuit node formed by coupling outputs of said transistors in said circuit branches, wherein said outputs of said transistors in said circuit branches are coupled together at said circuit node solely with a conducting wire.

43. The MISO amplifier of claim 25, wherein said input signals are simultaneously amplified and combined at a circuit node formed by coupling outputs of said transistors in said circuit branches, wherein said outputs of said transistors in said circuit branches are coupled together at said circuit node with substantially no resistive, inductive, or capacitive components.

44. The MISO amplifier of claim 25, wherein said input signals are simultaneously amplified and combined at a circuit node formed by coupling outputs of said transistors in said circuit branches, wherein said outputs of said transistors in said circuit branches are coupled together at said circuit node with no resistive, inductive, or capacitive components.

45. The MISO amplifier of claim 25, wherein said input signals are simultaneously amplified and combined at a circuit node formed by coupling outputs of said transistors in said circuit branches, wherein said outputs of said transistors in said circuit branches are coupled together at said circuit node with only parasitic resistive, inductive, or capacitive elements.

46. The MISO amplifier of claim 25, wherein said input signals are simultaneously amplified and combined at a circuit node formed by coupling outputs of said transistors in said circuit branches, wherein said outputs of said transistors in said circuit branches are coupled together at said circuit node with substantially no electrical isolation.

47. The MISO amplifier of claim 25, wherein said input signals are simultaneously amplified and combined at a circuit node formed by coupling outputs of said transistors in said circuit branches, wherein said outputs of said transistors in said circuit branches are coupled together at said circuit node with substantially no magnetic isolation.

48. The MISO amplifier of claim 25, wherein said input signals are simultaneously amplified and combined at a circuit node formed by coupling outputs of said transistors in said circuit branches, wherein said outputs of said transistors in said circuit branches are coupled together at said circuit node with substantially no electrical isolation and substantially no magnetic isolation.

49. The MISO amplifier of claim 25, wherein said MISO amplifier comprises a plurality of collector coupled or emitter coupled transistors.

50. The MISO amplifier of claim 25, wherein said MISO amplifier comprises a plurality of drain coupled or source coupled transistors.

51. The MISO amplifier of claim 25, wherein said MISO amplifier comprises a plurality of npn transistors.

52. The MISO amplifier of claim 25, wherein said MISO amplifier comprises a plurality of pnp transistors.

53. The MISO amplifier of claim 25, wherein said MISO amplifier comprises a plurality of npn and pnp transistors.

54. The MISO amplifier of claim 25, wherein said MISO amplifier comprises a plurality of NMOS transistors.

55. The MISO amplifier of claim 25, wherein said MISO amplifier comprises a plurality of PMOS transistors.

56. The MISO amplifier of claim 25, wherein said MISO amplifier comprises a plurality of NMOS and PMOS transistors.

57. A method of power amplification using a multiple input single output (MISO) amplifier, comprising:

receiving a plurality of input signals at inputs of said MISO, said MISO comprising a plurality of circuit branches coupled to said inputs, said circuit branches each comprising one or more transistors; and

simultaneously amplifying and combining said input signals to create an output signal of said MISO amplifier.

58. The method of claim 57, further comprising:

biasing said MISO amplifier.

59. The MISO amplifier of claim 58, wherein said biasing step comprises:

controlling one or more of output power efficiency, output linearity, and amplification stage protection.

60. The method of claim 57, further comprising:

harmonically shaping said output signal.

61. The MISO amplifier of claim 60, wherein said harmonically shaping step comprises:

wave-shaping said input signals.

62. The method of claim 60, wherein said harmonically shaping step comprises:

wave-shaping said output signal.

63. The method of claim 57, further comprising:

protecting said MISO amplifier.

64. The method of claim 63, wherein said protecting step comprises:

limiting current through said circuit branches.

65. The method of claim 57, further comprising:

dynamically controlling said transistors of said circuit branches to thereby transition operation of said transistors along an operational range that includes switching amplifier operation and current source amplifier operation.

66. The method of claim 57, further comprising:

controlling an input differential phase and a bias of said transistors based on requirements of said output signal.

67. The method of claim 57, wherein output voltages of said transistors in said circuit branches are substantially equal to an output voltage of said MISO amplifier for all operational instances of time of said MISO amplifier.

68. The method of claim 57, wherein said circuit branches each comprises one or more power amplification sub-stages.

69. The method of claim 68, wherein said power amplification sub-stages each comprises at least one of a pre-driver and a driver.

70. The method of claim 68, further comprising one or more pull-up impedances at an output of each of said power amplifier sub-stages for biasing of said each of said power amplifier sub-stages.

71. The method of claim 68, further comprising matching impedances at an output of each of said power amplifier sub-stages for enhancing power transfer from said each of said power amplifier sub-stages.

72. The method of claim 57, further comprising one or more non-linear amplifiers.

73. The method of claim 57, wherein said step of simultaneously amplifying and combining comprises simultaneously amplifying and combining said input signals at a circuit node formed by coupling outputs of said transistors in said circuit branches, wherein said outputs of said transistors in said circuit branches are coupled together at said circuit node with a conducting wire.

74. The method of claim 57, wherein said step of simultaneously amplifying and combining comprises simultaneously amplifying and combining said input signals at a circuit node formed by coupling outputs of said transistors in said circuit branches, wherein said outputs of said transistors in said circuit branches are coupled together at said circuit node solely with a conducting wire.

75. The method of claim 57, wherein said step of simultaneously amplifying and combining comprises simultaneously amplifying and combining said input signals at a circuit node formed by coupling outputs of said transistors in said circuit branches, wherein said outputs of said transistors in said circuit branches are coupled together at said circuit node with substantially no resistive, inductive, or capacitive components.

76. The method of claim 57, wherein said step of simultaneously amplifying and combining comprises simultaneously amplifying and combining said input signals at a circuit node formed by coupling outputs of said transistors in said circuit branches, wherein said outputs of said transistors in said circuit branches are coupled together at said circuit node with no resistive, inductive, or capacitive components.

77. The method of claim 57, wherein said step of simultaneously amplifying and combining comprises simultaneously amplifying and combining said input signals at a circuit node formed by coupling outputs of said transistors in said circuit branches, wherein said outputs of said transistors in said circuit branches are coupled together at said circuit node with only parasitic resistive, inductive, or capacitive elements.

78. The method of claim 57, wherein said step of simultaneously amplifying and combining comprises simultaneously amplifying and combining said input signals at a circuit node formed by coupling outputs of said transistors in said circuit branches, wherein said outputs of said transistors in said circuit branches are coupled together at said circuit node with substantially no electrical isolation.

79. The method of claim 57, wherein said step of simultaneously amplifying and combining comprises simultaneously amplifying and combining said input signals at a circuit node formed by coupling outputs of said transistors in said circuit branches, wherein said outputs of said transistors in said circuit branches are coupled together at said circuit node with substantially no magnetic isolation.

80. The method of claim 57, wherein said step of simultaneously amplifying and combining comprises simultaneously amplifying and combining said input signals at a circuit node formed by coupling outputs of said transistors in said circuit branches, wherein said outputs of said transistors in said circuit branches are coupled together at said circuit node with substantially no electrical isolation and substantially no magnetic isolation.

81. The method of claim 57, wherein said MISO amplifier comprises a plurality of collector coupled or emitter coupled transistors.

82. The method of claim 57, wherein said MISO amplifier comprises a plurality of drain coupled or source coupled transistors.

83. The method of claim 57, wherein said MISO amplifier comprises a plurality of npn transistors.

84. The method of claim 57, wherein said MISO amplifier comprises a plurality of pnp transistors.

85. The method of claim 57, wherein said MISO amplifier comprises a plurality of npn and pnp transistors.

86. The method of claim 57, wherein said MISO amplifier comprises a plurality of NMOS transistors.

87. The method of claim 57, wherein said MISO amplifier comprises a plurality of PMOS transistors.

88. The method of claim 57, wherein said MISO amplifier comprises a plurality of NMOS and PMOS transistors.