Channel-select decimation filter with programmable bandwidth

• US 20070027943A1
• Filed: 07/26/2005
• Published: 02/01/2007
• Est. Priority Date: 07/26/2005
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Ibrahim, Brima, Jensen, Henrik
• Granted Patent: US 7,685,217 B2
• Time in Patent Office: Days
• US Class Current: 708/300
• CPC Class Codes: H03H 17/0664 where the output-delivery frequency is lower than the input sampling frequency, i.e. decimation
• CPC Class Codes: H03H 17/0671 Cascaded integrator-comb [CIC] filters
• CPC Class Codes: H04L 27/38 Demodulator circuits; Receiver circuits

Abstract

A channel-select decimation filter capable of operating in multiple bandwidth modes includes a first low pass filter stage, a variable gain stage, a subtraction module a second low pass filter stage and a down-sampling module. The first low pass filter stage includes a first programmable delay module for filtering input signals to produce first low pass filtered signals. The variable gain stage applies a programmable gain to the input signals to produce gained input signals. The subtraction module subtracts the first low pass filtered signals from the gain input signals to produce first stage signals. The second low pass filter stage includes a second programmable delay module for filtering the first stage signals to produce channel-selected signals. The first programmable delay module, second programmable delay module and programmable gain are programmed to implement one of the multiple bandwidth modes.

Claims

1. A channel-select decimation filter capable of operating in multiple bandwidth modes, the channel-select decimation filter comprises:

a first low pass filter stage including a first programmable delay module and operably coupled to filter input signals to produce first low pass filtered signals;

a variable gain stage operably coupled to apply a programmable gain to the input signals to produce gained input signals;

subtraction module operably coupled to subtract the first low pass filtered signals from the gain input signals to produce first stage signals;

a second low pass filter stage including a second programmable delay module operably coupled to filter the first stage signals to produce channel-selected signals; and

a down-sampling module operably coupled to decimate the channel-selected signals to produce down-sampled channel-selected signals; and

wherein the first programmable delay module, the second programmable delay module and the programmable gain are programmed to implement one of the multiple bandwidth modes.

2. The channel-select decimation filter of claim 1, wherein the first low pass filter stage comprises:

a plurality of cascaded low pass filters operably coupled to filter the input signals to produce low pass filtered signals; and

wherein the first programmable delay module is operably coupled to delay the filtered signals to produce the first low pass filtered signals.

3. The channel-select decimation filter of claim 2, wherein the second low pass filter stage comprises:

a plurality of cascaded low pass filters operably coupled to filter the first stage signals to produce filtered first stage signals; and

wherein the second programmable delay module is operably coupled to delay the filtered first stage signals to produce the channel-selected signals.

4. The channel-select decimation filter of claim 3, further comprising:

a plurality of cascaded integrators; and

a plurality of cascaded differentiators;

wherein a first select number of the plurality of cascaded integrators are selected to form the first programmable delay module;

wherein a second select number of the plurality of cascaded differentiators are selected to form the second programmable delay module; and

wherein the first select number is equal to the second select number and is chosen to provide the channel-select filter with a bandwidth corresponding to a select bandwidth mode of the multiple bandwidth modes.

5. The channel-select decimation filter of claim 4, wherein each of the cascaded differentiators has a programmable delay line programmed to provide the channel-select filter with the bandwidth corresponding to the select bandwidth mode.

6. The channel-select decimation filter of claim 3, wherein each of the plurality of cascaded low pass filters comprises a comb filter.

7. The channel-select decimation filter of claim 1, wherein the variable gain stage comprises:

a variable gain module operably coupled to apply the programmable gain to the input signals to adjust a magnitude of the input signals to produce magnitude adjusted input signals; and

a delay module operably coupled to delay the magnitude adjusted input signals to produce the gained input signals.

8. The channel-select decimation filter of claim 1, wherein the programmable gain has a select value of multiple values selected to provide the channel-select filter with a bandwidth corresponding to a select bandwidth mode of the multiple bandwidth modes.

9. A radio receiver, comprising:

a low noise amplifier operably coupled to amplify inbound radio frequency (RF) signals to produce amplified inbound RF signals;

a down conversion module operably coupled to convert the amplified inbound RF signals into low intermediate frequency (IF) signals;

an analog to digital converter operably coupled to convert the low IF signals into digital low IF signals; and

a digital demodulator operably coupled to convert the digital low IF signals into inbound symbols, wherein the digital demodulator includes;

a baseband conversion module operably coupled to convert the digital low IF signals into digital baseband signals;

a channel-select decimation filter operably coupled to filter the digital baseband signals to produce channel-selected signals in a select bandwidth mode of multiple bandwidth modes, wherein the channel-select decimation filter includes;

a first low pass filter stage including a first programmable delay module operably coupled to filter the digital baseband signals to produce first low pass filtered signals;

a variable gain stage operably coupled to apply a programmable gain to the input signals to produce gained input signals;

a subtraction module operably coupled to subtract the first low pass filtered signals from the gain input signals to produce first stage signals;

a second low pass filter stage including a second programmable delay module and operably coupled to filter the first stage signals to produce channel-selected signals; and

a down-sampling module coupled to decimate the channel-selected signals to produce down-sampled channel-selected signals;

wherein the first programmable delay module, the second programmable delay module and the programmable gain are programmed to implement the select bandwidth mode; and

a demodulation module operably coupled to produce the inbound symbols from the channel-selected signals.

10. The radio receiver of claim 9, wherein the first low pass filter stage comprises:

a plurality of cascaded low pass filters operably coupled to filter the input signals to produce low pass filtered signals; and

wherein the first programmable delay module is operably coupled to delay the filtered signals to produce the first low pass filtered signals.

11. The radio receiver of claim 10, wherein the second low pass filter stage comprises:

a plurality of cascaded low pass filters operably coupled to filter the first stage signals to produce filtered first stage signals; and

wherein the second programmable delay module is operably coupled to delay the filtered first stage signals to produce the channel-selected signals.

12. The radio receiver of claim 11, further comprising:

a plurality of cascaded integrators; and

a plurality of cascaded differentiators;

wherein a first select number of the plurality of cascaded integrators are selected to form the first programmable delay module;

wherein a second select number of the plurality of cascaded differentiators are selected to form the second programmable delay module; and

wherein the first select number is equal to the second select number and is chosen to provide the channel-select filter with a bandwidth corresponding to the select bandwidth mode.

13. The radio receiver of claim 12, wherein each of the cascaded differentiators has a programmable delay line programmed to provide the channel-select filter with the bandwidth corresponding to the select bandwidth mode.

14. The radio receiver of claim 9, wherein the programmable gain has a select value of multiple values selected to provide the channel-select filter with a bandwidth corresponding to the select bandwidth mode.

15. A method for filtering and decimating input signals in a select bandwidth mode of multiple bandwidth modes, comprising the steps of:

programming a first programmable delay, a second programmable delay and a programmable gain for the select bandwidth mode;

first filtering the input signals using the first programmable delay to produce first low pass filtered signals;

applying the programmable gain to the input signals to produce gained input signals;

subtracting the first low pass filtered signals from the gained input signals to produce first stage signals;

second filtering the first stage signals using the second programmable delay to produce channel-selected signals; and

down-sampling the channel-selected signals to produce down-sampled channel-selected signals.

16. The method of claim 15, wherein the first filtering further comprises:

low pass filtering the input signals to produce filtered signals; and

delaying the filtered signals to produce the first low pass filtered signals using the first programmable delay.

17. The method of claim 16, wherein the second filtering further comprises:

low pass filtering the first stage signals to produce filtered first stage signals; and

delaying the filtered first stage signals to produce the channel-selected signals using the second programmable delay.

18. The method of claim 17, wherein the programming further comprises:

selecting a first select number of a plurality of cascaded integrators to form the first programmable delay;

selecting a second select number of a plurality of cascaded differentiators to form the second programmable delay; and

wherein the first select number is equal to the second select number and the first number is chosen to provide a filter bandwidth corresponding to the select bandwidth mode.

19. The method of claim 17, wherein the programming further comprises

programming each of the cascaded differentiators with a programmable delay line to provide the channel-select filter with the bandwidth corresponding to the select bandwidth mode.

20. The method of claim 15, wherein the programming further comprises:

p1 programming the programmable gain with a select value of multiple values selected to provide a filter bandwidth corresponding to the select bandwidth mode.