Storage device, computer system, and storage system

• US 20070028035A1
• Filed: 07/27/2006
• Published: 02/01/2007
• Est. Priority Date: 07/29/2005
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Nishihara, Toshiyuki
• Granted Patent: US 9,183,132 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control

Abstract

A storage device enabling realization of a new storage configuration enabling apparent elimination of the overhead and enabling high speed access all the time particularly when constructing a high parallel configured high speed flash memory system, that is, a storage device having a flash memory as a main storage and having the function of rewriting at least a partial region of the flash memory by additional writing update data in an empty region and invalidating original data and, at the time of standby of the device where there is no access from the outside, performing processing for automatically restoring the invalidated region to an empty region, and a computer system and a storage system using the same.

Claims

1. A storage device comprising:

a flash memory as a main storage, and

a control unit,

wherein the control unit rewrites at least a partial region in the flash memory by additional writing update data in an empty region and invalidating the original data and

automatically restores an invalidated region to an empty region at the time of standby of the device with no access from the outside as restoration processing.

2. A storage device as set forth in claim 1, wherein

the flash memory has a plurality of erasure blocks as block erasure units, each erasure block including a plurality of page regions as write units independent from each other, and

the control unit includes, as the restoration processing, processing backing up the data of a valid page region remaining in an erasure block including an invalid page region to be restored to an erased empty region of another erasure block.

3. A storage device as set forth in claim 1, wherein, when access occurs to data stored in the storage device from the outside and the restoration processing is underway, the control unit interrupts the restoration processing and performs processing to respond to the access.

4. A storage device as set forth in claim 3, wherein, when interrupting the restoration processing, the control unit stores progress information of the restoration processing in a register or a memory in the device and, when the access ends, restarts the restoration processing with reference to the progress information.

5. A storage device as set forth in claim 4, wherein at least a portion of the progress information of the restoration processing is recorded in a nonvolatile RAM.

6. A storage device as set forth in claim 5, wherein the nonvolatile RAM is at least one of a ferro-electric memory (FeRAM), a ferro-magnetic memory (MRAM), an ovonic unified memory (OUM), and a magnetoresistance effect memory (RRAM).

7. A storage device as set forth in claim 4, wherein the storage device has a processing unit inside it, the processing unit executes the restoration processing at the time of standby, the processing unit is interrupted when there is an access from the outside, and the processing unit interrupts the restoration processing and starts the access processing according to the interruption event.

8. A storage device as set forth in claim 2, wherein the control unit divides the restoration processing of one or a plurality of invalid page regions existing in one erasure block into a plurality of steps and executes a portion thereof at the time of standby of the storage device where there is no access from the outside.

9. A storage device comprising:

a flash memory as a main storage, and

a control unit,

wherein the control unit rewrites at least a partial region in the flash memory by additional writing update data to an empty region and invalidating the original data and

restores the invalidated region to an empty region in response to a predetermined command from the outside as restoration processing.

10. A storage device as set forth in claim 9, wherein

the flash memory has a plurality of erasure blocks as block erasure units, each erasure block including a plurality of page regions as write units independent from each other, and

the restoration processing includes processing backing up the data of a valid page region remaining in an erasure block including an invalid page region to be restored to an erased empty region of another erasure block.

11. A storage device as set forth in claim 9, wherein the control unit stores progress information of the restoration processing in a register or memory in the device when interrupting the restoration processing in response to a predetermined command from the outside and restarts the restoration processing with reference to the progress information when receiving an execution command of the restoration processing again.

12. A storage device as set forth in claim 11, wherein at least a portion of the progress information of the restoration processing is recorded in a nonvolatile RAM.

13. A storage device as set forth in claim 12, wherein the nonvolatile RAM is at least one of a ferro-electric memory (FeRAM), a ferro-magnetic memory (MRAM), an ovonic unified memory (OUM), and a magnetoresistance effect memory (RRAM).

14. A storage device as set forth in claim 10, wherein the control unit divides the restoration processing of one or more invalid page regions existing in one erasure block into a plurality of steps and executes a portion thereof in response to a predetermined command from the outside.

15. A storage device comprising:

a flash memory as a main storage,

a cache memory, and

a control unit,

wherein the control unit rewrites at least a partial region in the flash memory by additional writing update data to an empty region and invalidating the original data and

performs at least a portion of the processing for restoring the invalidated data to an empty region in parallel during a term where access from the outside hits the cache memory and the cache is accessed as restoration processing.

16. A storage device as set forth in claim 15, wherein

the flash memory has a plurality of erasure blocks as block erasure units, each erasure block including a plurality of page regions as write units independent from each other, and

the restoration processing includes processing backing up the data of a valid page region remaining in an erasure block including an invalid page region to be restored to an erased empty region of another erasure block.

17. A storage device as set forth in claim 15, wherein, when access from the outside misses the cache memory and the restoration processing is underway, the control unit interrupts the restoration processing and performs processing to respond to the access.

18. A storage device as set forth in claim 17, wherein the control unit stores progress information of the restoration processing in a register or memory in the device when interrupting the restoration processing and restarts the restoration processing with reference to the progress information when the access ends.

19. A storage device as set forth in claim 17, wherein at least a portion of the progress information of the restoration processing is recorded in a nonvolatile RAM.

20. A storage device as set forth in claim 18, wherein the nonvolatile RAM is at least one of a ferro-electric memory (FeRAM), a ferro-magnetic memory (MRAM), an ovonic unified memory (OUM), and a magnetoresistance effect memory (RRAM).

21. A storage device as set forth in claim 20, wherein the control unit divides the restoration processing of one or more invalid page regions existing in one erasure block into a plurality of steps and executes a portion thereof while access from the outside hits the cache memory and the cache is accessed.

23. A computer system as set forth in claim 21, wherein

the flash memory has a plurality of erasure blocks as block erasure units, each erasure block including a plurality of page regions as write units independent from each other, and

the restoration processing includes processing backing up the data of a valid page region remaining in an erasure block including an invalid page region to be restored to an erased empty region of another erasure block.

27. A computer system as set forth in claim 23, wherein the host computer divides the restoration processing of one or more invalid page regions existing in one erasure block into a plurality of steps and executes a portion thereof at the time of standby where there is no access to the data storage from the outside.

22. A computer system comprising:

a host computer, and

a nonvolatile data storage including a flash memory as a main storage and storing various data handled in the host computer,

wherein the host computer rewrites at least a partial region in the flash memory by additional writing update data to an empty region and invalidating the original data and

executes processing for restoring the invalidated region to an empty region at the time of standby where there is no data processing request for the data storage other than that.

24. A computer system as set forth in claim 22, wherein the host computer temporarily interrupts the restoration processing when a request for data access to the data storage occurs and the restoration processing is underway and, when temporarily interrupting it, stores progress information of the restoration processing in a register or a memory inside the computer system and restarts and continues the processing with reference to the progress information when executing the restoration processing again.

25. A computer system as set forth in claim 24, wherein at least a portion of the progress information of the restoration processing is recorded in a nonvolatile RAM.

26. A computer system as set forth in claim 25, wherein the nonvolatile RAM is at least one of a ferro-electric memory (FeRAM), a ferro-magnetic memory (MRAM), an ovonic unified memory (OUM), and a magnetoresistance effect memory (RRAM).

28. A storage system comprising:

a flash memory as a storage medium, and

a control circuit,

wherein the flash memory has erasure blocks as block erasure units, each erasure block including a plurality of data regions, and

the control circuit reads out at least a portion of the region for each data region before erasing the erasure block, judges whether or not valid data is recorded in the data region from the read out value, and, when valid data is recorded as a result of judgment, copies the data of the data region to another erasure block.

29. A storage system as set forth in claim 28, wherein the control circuit reads out a flag value described in a portion of the data region and judges the data is valid when the flag value is a predetermined value.

30. A storage system as set forth in claim 28, wherein the control circuit reads out a handle value described in a portion of the data region, compares correspondence between a physical address on the memory of the data and the handle value with a predetermined table, and judges the data as valid when they coincide.