Data processing system

• US 20070028038A1
• Filed: 08/19/2004
• Published: 02/01/2007
• Est. Priority Date: 09/04/2003
• Status: Active Grant

• Current Assignee: Network System Technologies LLC
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Van Der Wolf, Pieter, Boonstra, Johannes, Van Eijdhoven, Josephus
• Granted Patent: US 7,870,347 B2
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 13/1663 Access to shared memory

Abstract

The disclosed data processing system comprises a memory means (SDRAM), a plurality of data processing means (IP) provided for accessing to said memory means (SDRAM), and a communication interface means coupled between said memory means (SDRAM) and said plurality of data processing means (IP), said communication interface means including a network of nodes (H 11, H 12, H2), each node comprising at least one slave port (s) for receiving a memory access request from a data processing means (IP) or from a previous node and at least one master port (m) for issuing a memory access request to a next node or to said memory means (SDRAM) in accordance with the memory access request received at said slave port (s), wherein said at least one slave port (s) is connected to a master port (m) of a previous node or to one of said data processing means (IP) and said at least one master port (m) is connected to a slave port (s) of a next node or to said memory means (SDRAM).

Claims

1. A data processing system, comprising a memory means (SDRAM) and a plurality of data processing means (IP) provided for accessing to said memory means (SDRAM), characterized by a communication interface means coupled between said memory means (SDRAM) and said plurality of data processing means (IP), said communication interface means including a network of nodes (H₁₁, H₁₂, H₂), each node comprising at least one slave port (s) for receiving a memory access request from a data processing means (IP) or from a previous node and at least one master port (m) for issueing a memory access request to a next node or to said memory means (SDRAM) in accordance with the memory access request received at said slave port (s), wherein said at least one slave port (s) is connected to a master port (m) of a previous node or to one of said data processing means (IP) and said at least one master port (m) is connected to a slave port (s) of a next node or to said memory means (SDRAM).

2. The data processing system according to claim 1, characterized in that at each node means the number of said slave ports (s) is higher than the number of said master ports (m).

3. The data processing system according to claim 1, characterized in that said network of node means (H₁₁, H₁₂, H₂) is hierarchically structured.

4. The data processing system according to claim 3, characterized in that said plurality of node means (H₁₁, H₁₂, H₂) are arranged in a directed acyclic graph structure.

5. The data processing system according to claim 4, characterized in that said plurality of node means (H₁₁, H₁₂, H₂) are arranged in a tree structure.

6. The data processing system according to claim 1, characterized in that said plurality of node means (H₁₁, H₁₂, H₂) include n groups of node means with n≧

2, wherein each of the slave ports (s) of the node means (H₁₁) of a first group is connected to one of said plurality of data processing means (IP), the master ports (m) of the node means (H₂) of the n^th group are coupled to said memory means (SDRAM), and each of the slave ports (s) of the node means (H₂) of the n^th group is connected to a master port (m) of the node means (H₁₁) of the (n−

1)^th group.

7. The data processing system according to claim 1, characterized in that said node means (H₁₁, H₁₂, H₂) are hubs.

8. The data processing system according to claim 1, characterized in that said communication interface means further includes at least one local memory unit (MEM) adapted to be selectively accessed to by a memory access request.

9. The data processing system according to claim 8, characterized in that at least one node means (H₁₁, H₁₂, H₂) further comprises at least one memory port (mp) to which a local memory unit (MEM) is connected.

10. The data processing system according to claim 8, characterized in that said communication interface means includes a cache controller means for controlling at least a section of the local memory unit(s) (MEM) as a cache memory.

11. The data processing system according to claim 1, characterized in that said communication interface means further includes at least one synchronization means for streaming communication between data processing means (IP).

12. The data processing system according to claim 11, characterized in that at least one node means (H₁₁, H₁₂, H₂) includes said synchronization means for streaming communication between the data processing means (IP) directly or indirectly coupled to said node means.

13. The data processing system according to claim 8, characterized in that the local memory unit(s) (MEM) is (are) configured to provide the storage means for a first-in/first-out function and said synchronization means comprises a first-in/first-out administration means for controlling said local memory unit(s) (MEM).

14. The data processing system according to claim 1, characterized in that said communication interface means is provided on a single chip (C).

15. The data processing system according to claim 14, characterized in that at least a part of said plurality of data processing means (IP) is additionally provided on said single chip (C).