Memory device

• US 20070028071A1
• Filed: 11/14/2005
• Published: 02/01/2007
• Est. Priority Date: 07/27/2005
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Takebe, Yoshimasa, Nodomi, Akira
• Granted Patent: US 7,434,023 B2
• Time in Patent Office: Days
• US Class Current: 711/202
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Abstract

A memory device that can handle various transmission-source devices and transmission-destination devices without modifying the hardware configuration. The memory device is used to transmit and receive data, and includes a data buffer for storing data output from a data-transmission source and outputting the data to a data-transmission destination serving as the data output destination; a transmission-source address converter for performing arrangement processing on the data output from the data-transmission source when the data-transmission source is a device that passively outputs data; and a transmission-destination address converter for performing arrangement processing on the data to be input to the data-transmission destination when the data-transmission destination is a device to which data is passively input.

Claims

1. A memory device for use in transmission and reception of data, comprising:

a data buffer for storing data output from a data-transmission source and for outputting the data to a data-transmission destination serving as an output destination of the data;

a transmission-source address converter for performing arrangement processing on the data output from the data-transmission source when the data-transmission source is a device that passively outputs data; and

a transmission-destination address converter for performing arrangement processing on the data to be input to the data-transmission destination when the data-transmission destination is a device to which data is passively input.

2. The memory device according to claim 1, wherein the data-transmission source is one of a CPU and a memory;

and

when the data-transmission source is the memory, the transmission-source address converter performs the arrangement processing.

3. The memory device according to claim 2, wherein the CPU also serves as the data-transmission destination.

4. The memory device according to claim 2, wherein the memory also serves as the data-transmission destination.

5. The memory device according to claim 1, wherein the data-transmission destination is one of a CPU and a memory;

and

when the data-transmission destination is the memory, the transmission-destination address converter performs the arrangement processing.

6. The memory device according to claim 1, wherein the arrangement processing is processing for consecutively transferring the data.

7. The memory device according to claim 1, wherein the arrangement processing is processing for transferring the data while maintaining a fixed spacing between data items of the data.

8. The memory device according to claim 1, wherein the arrangement processing is processing in which a plurality of data blocks maintaining a fixed spacing between data items of the data are formed, and each data block is transferred while maintaining a fixed spacing.

9. The memory device according to claim 1, wherein the transmission-source address converter and the transmission-destination address converter perform different arrangement processing.

10. The memory device according to claim 1, wherein the data buffer is configured to perform first-in first-out control.

11. The memory device according to claim 1, further comprising an address controller for performing sequence control of the data buffer based on a write pointer indicating a write destination address of the data in the data buffer by inputting a write signal and a read pointer indicating a read source address of the data in the data buffer by inputting a read signal.

12. The memory device according to claim 11, further comprising:

a write-pointer generator for generating the write pointer; and

a read-pointer generator for generating the read pointer.