Semiconductor device

• US 20070029543A1
• Filed: 08/02/2006
• Published: 02/08/2007
• Est. Priority Date: 08/04/2005
• Status: Abandoned Application

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Ninomiya, Hitoshi, Miura, Yoshinao
• Application Number:
  US11/497,342
• Publication Number:
  US 20070029543A1
• Time in Patent Office: Days
• US Class Current: 257/25
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

To enhance the super-junction effect of a semiconductor device having the super-junction structure and prevent lowering in the breakdown voltage, a semiconductor device described herein has a first-conductivity-type substrate having an element forming region having a gate electrode and a source electrode formed therein, and a periphery region formed around the element forming region and having an element isolating region formed therein; and a parallel p-n layer having n-type drift regions and p-type column regions alternately arranged therein, formed along the main surface of the substrate, as extending from the element forming region to the periphery region, wherein, in the periphery region, a plurality of p-type column regions are provided outwardly from the element-forming region; and the gate electrode is a trench gate buried in the substrate, being formed so as to surround the p-type column regions also in the periphery region similarly to as in the element forming region.

Claims

1. A semiconductor device comprising:

a first-conductivity-type substrate having an element forming region having a gate electrode and a source electrode formed therein, and a periphery region formed around said element forming region; and

a parallel p-n layer having first-conductivity-type drift regions and second-conductivity-type column regions alternately arranged therein, formed along the main surface of said substrate, as extending from said element forming region to said periphery region,

wherein said gate electrode is a trench gate buried in said substrate, said trench gate being formed so as to surround said column regions in a plan view in said element forming region and said periphery region.

2. The semiconductor device according to claim 1, wherein at least one of said column regions formed in the periphery region has a depth not smaller than the depth of the column regions formed in said element forming region.

3. The semiconductor device according to claim 1, wherein in said element forming region, a second-conductivity-type base region is formed in a region along the main surface of said substrate and surrounded by said trench gate, and

wherein in said periphery region, said second-conductivity-type base region is not formed in a region along the main surface of said substrate.

4. The semiconductor device according to claim 1, wherein said source electrode is formed so that the end portion thereof covers a part of said periphery region.

5. The semiconductor device according to claim 1, wherein the trench gate formed in said periphery region is formed so as to surround the individual column regions formed in said periphery region in a plan view.

6. The semiconductor device according to claim 1, wherein in said periphery region, a gate interconnection pattern is formed in the outermost region of said gate electrode, and

said trench gate is connected to said gate interconnection pattern.

7. The semiconductor device according to claim 1, wherein said first-conductivity-type drift regions of said parallel p-n layer are coupled together to be formed a reticular pattern.

8. A method of fabricating a semiconductor device, which contains a semiconductor substrate having an element forming region and a peripheral region adjoining said element forming region, said element forming region having a gate electrode, a first-conductivity-type source region and a second-conductivity-type base region, comprising:

forming a first-conductivity-type drift region in one surface of said semiconductor substrate,

forming a field electrode on said semiconductor substrate in a portion of said peripheral region,

forming a plurality of second-conductivity-type column regions in said first-conductivity-type drift region after forming said field electrode.

9. The method of fabricating a semiconductor device according to claim 8, further comprising:

forming a trench in said first-conductivity-type drift region; and

forming a gate insulating film on a inner surface of said trench,

wherein said gate electrode is formed on said gate insulating film in said trench and electrically connected with said field electrode.

10. The method of fabricating a semiconductor device according to claim 9, wherein each of said plurality of second-conductivity-type column regions is surrounded by said gate electrode in a plan view, respectively.