Scalable high performance carbon nanotube field effect transistor

• US 20070029612A1
• Filed: 08/02/2005
• Published: 02/08/2007
• Est. Priority Date: 08/02/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sandhu, Gurtej
• Granted Patent: US 7,687,841 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H10K 10/464 Lateral top-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 10/481 characterised by the gate conductors
• CPC Class Codes: H10K 85/221 Carbon nanotubes
• CPC Class Codes: Y10S 977/742 Carbon nanotubes, CNTs

Abstract

A structure and fabrication process for a carbon nanotube field effect transistor is disclosed herein. The structure employs an asymmetric gate which is closer to the source and farther from the drain, which helps to minimize “off current” drain leakage when the drain is biased and the gate is otherwise off. In an embodiment, the source and drain are preferably self aligned to the gate, and preferably the gate is first defined as a conductive sidewall to an etched pad. Dielectric sidewalls are then defined over the gate, which in turn defines the positioning of the source and drain in a predetermined spatial relationship to the gate. In a preferred embodiment, the source and drain comprise conductive sidewalls buttressing the dielectric sidewalls. The channel of the device preferably comprises randomly oriented carbon nanotubes formed on an insulative substrate and isolated from the gate by an insulative layer. In a preferred embodiment, the carbon nanotubes are exposed via the dielectric sidewall etch, thus ensuring the gate'"'"'s self alignment with the subsequently-formed source and drain.

Claims

1. A transistor, comprising:

a channel formed of at least one carbon nanotube, wherein the channel is in contact with a source and with a drain of the transistor;

a dielectric material proximate to the channel; and

a gate proximate to the dielectric material, wherein the gate is positioned closer to the source than to the drain, and wherein the source and drain are self aligned with respect to the gate.

2. The transistor of claim 1, wherein the channel comprises a plurality of carbon nanotubes, wherein ends of the plurality of carbon nanotubes are in contact with the source and the drain.

3. The transistor of claim 1, wherein the gate comprises a sidewall on the edge of a pad, and wherein the source and drain are self aligned with respect to the gate and to the pad.

4. The transistor of claim 1, wherein the at least one carbon nanotube comprises a single-walled carbon nanotube.

5. The transistor of claim 1, wherein the at least one carbon nanotube comprises a multi-walled carbon nanotube.

6. The transistor of claim 1, wherein the gate is over the channel.

7. The transistor of claim 1, wherein the source and drain comprise sidewalls formed on an edge of at least the channel.

8. The transistor of claim 7, wherein the source and drain are further formed on a sidewall of the dielectric material.

9. A transistor, comprising:

a channel formed of at least one carbon nanotube, wherein the ends of at least one nanotube are in contact with a source and with a drain of the transistor; and

a gate for imparting an electric field to the channel, wherein the gate is asymmetric with respect to the source and the drain, and wherein the gate is comprised of a sidewall.

10. The transistor of claim 9, wherein the gate is formed on one edge of a pad.

11. The transistor of claim 10, wherein the source and drain are self aligned with respect to the gate and to the pad.

12. The transistor of claim 9, wherein the channel comprises a plurality of carbon nanotubes.

13. The transistor of claim 9, wherein the at least one carbon nanotube comprises either a single-walled carbon nanotube or a multi-walled carbon nanotube.

14. The transistor of claim 9, wherein the gate is over the channel.

15. The transistor of claim 9, wherein the source and drain comprise sidewalls formed on an edge of at least the channel.

16. The transistor of claim 15, wherein the source and drain are further formed on a sidewall of the dielectric material.

17. A transistor, comprising:

a first dielectric material;

a channel formed of at least one carbon nanotube on the first dielectric material;

a second dielectric material on the channel;

a source and a drain of the transistor, wherein both the source and the drain contact edges of the first dielectric material, the channel, and the second dielectric material; and

a gate formed on the second dielectric material, wherein the gate is formed closer to the source than to the drain.

18. The transistor of claim 17, wherein the gate is formed on one edge of a pad.

19. The transistor of claim 17, wherein the source and drain are self aligned with respect to the gate.

20. The transistor of claim 17, wherein the gate is over the channel.

21. The transistor of claim 17, wherein the source and drain comprise sidewalls formed on edges of the first dielectric material, the channel, and the second dielectric material.

22. A transistor, comprising:

a channel region having edges, the channel region comprising a channel formed of at least one carbon nanotube and a dielectric layer on top of and under the channel;

a source and drain formed on the edges of the channel region; and

a gate for imparting an electric field to the channel.

23. The transistor of claim 22, wherein the gate is asymmetric with respect to the source and drain.

24. The transistor of claim 22, wherein the gate is formed as a sidewall on the edge of a pad.

25. The transistor of claim 22, wherein the source and drain comprise sidewalls formed on the edges of the channel region.

26. The transistor of claim 22, wherein the source and drain are self aligned.

27. The transistor of claim 22, wherein the source and drain are formed with out the use of a patterning step.

28. The transistor of claim 22, wherein the gate is formed without the use of a patterning step.

29. A method for forming a transistor, comprising:

forming a channel of at least one carbon nanotube on a substrate;

forming a dielectric over the channel;

defining a gate over the dielectric;

etching the dielectric to expose the channel; and

forming source and drain regions in contact with the exposed portions of the channel.

30. The method of claim 29, wherein the channel is formed by spinning the carbon nanotubes on the substrate.

31. The method of claim 29, wherein the gate is formed without being defined by a patterning step.

32. The method of claim 29, wherein the source and drain are formed without being defined by a patterning step.

33. The method of claim 29, wherein the gate, the source, and the drain all comprise sidewalls.

34. The method of claim 29, wherein the gate is asymmetric with the source and drain.

35. The method of claim 34, wherein the gate is formed on the edge of a pad.

36. The method of claim 29, wherein the channel is formed by deposition and etching.

37. The method of claim 29, wherein the at least one carbon nanotube comprises a single-walled carbon nanotube.

38. The method of claim 29, wherein the at least one carbon nanotube comprises a multi-walled carbon nanotube.

39. A method for forming a transistor, comprising:

forming a channel of at least one carbon nanotube;

forming a gate asymmetrically with respect to the channel; and

forming source and drain regions in contact with the channel, wherein the source and drain regions are formed after formation of the gate and without a patterning step.

40. The method of claim 39, wherein the channel is formed by spinning the carbon nanotubes on the substrate.

41. The method of claim 40, wherein the carbon nanotubes are provided in a solvent when spun on the substrate.

42. The method of claim 39, wherein the gate is formed without being defined by a patterning step.

43. The method of claim 39, wherein the gate, the source, an the drain all comprise sidewalls.

44. The method of claim 43, wherein the gate is formed on the edge of a pad.

45. A method for forming a transistor, comprising:

forming a channel of at least one carbon nanotube, wherein the at least one nanotube comprises edges;

forming source and drain regions in contact with the edges of the at least one nanotube; and

forming a gate, wherein the gate is positioned closer to the source region than to the drain region.

46. The method of claim 45, wherein the gate is over the channel.

47. The method of claim 45, wherein the source and drain regions are self aligned to the gate.

48. A method for forming a transistor, comprising:

forming a channel of at least one carbon nanotube;

forming a pad over the channel;

forming a gate on at least one side of the pad; and

forming a source and drain in contact with the channel, wherein the source and drain are self aligned with respect to the gate and the pad.