Gated nanorod field emitter structures and associated methods of fabrication

• US 20070029911A1
• Filed: 07/19/2005
• Published: 02/08/2007
• Est. Priority Date: 07/19/2005
• Status: Active Grant

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Zhang, Anping, Denault, Lauraine, Lee, Ji, Corderman, Reed, Balch, Joleyn, Hudspeth, Heather, Rohling, Renee
• Granted Patent: US 7,326,328 B2
• Time in Patent Office: Days
• US Class Current: 313/309
• CPC Class Codes: H01J 1/304 Field-emissive cathodes
• CPC Class Codes: H01J 3/021 Electron guns using a field emission, photo emission, or secondary emission electron source
• CPC Class Codes: H01J 9/025 of field emission cathodes

Abstract

The present invention relates to gated nanorod field emission devices, wherein such devices have relatively small emitter tip-to-gate distances, thereby providing a relatively high emitter tip density and low turn on voltage. Such methods employ a combination of traditional device processing techniques (lithography, etching, etc.) with electrochemical deposition of nanorods. These methods are relatively simple, cost-effective, and efficient; and they provide field emission devices that are suitable for use in x-ray imaging applications, lighting applications, flat panel field emission display (FED) applications, etc.

Claims

1. A method comprising the steps of:

a) providing a thin film material comprising;

i) a substrate;

ii) a dielectric layer on the substrate; and

iii) a conductive film on the dielectric layer;

b) lithographically-patterning a patternable material deposited onto the conductive film so as to selectively remove portions of this material;

c) selectively etching the conductive film and dielectric layer in regions where the patternable has been removed so as to form microcavities;

d) depositing Al inside the microcavities to form Al mesas;

e) anodizing the Al mesas to form localized nanoporous AAO templates; and

f) electrochemically-depositing nanorods in the nanopores of the AAO templates to yield at least one gated nanorod field emission device.

2. The method of claim 1, further comprising a step of etching back the AAO to more fully expose the nanorod field emitters.

3. The method of claim 1, wherein the substrate comprises a material selected from the group consisting of semiconductors, glasses, molecular solids, metals, ceramics, polymers, and combinations thereof.

4. The method of claim 1, wherein the conductive film comprises a material selected from the group consisting of (a) metal selected from the group consisting of Nb, Pt, Al, W, Mo, Ti, Ni, Cr, TiW, and combinations thereof;

(b) semiconductor material selected from the group consisting of highly-doped Si, GaN, GaAs, SiC, doped poly Si, doped amorphous Si, and combinations thereof; and

(c) combinations thereof.

5. The method of claim 1, wherein the dielectric layer comprises a material selected from the group consisting of SiO₂, SiN_x, epi-i-SiC, A1₂O₃, undoped wide bandgap material, and combinations thereof.

6. The method of claim 1, where the step of depositing Al involves the use of a metal evaporation technique.

7. The method of claim 1, wherein the step of electrochemically-depositing involves the deposition of a material selected from the group consisting of Pt, Pd, Ni, Au, Ag, Cu, Zn, ZnO, MoO₃/Mo₂O₃, and combinations thereof.

8. A method comprising the steps of:

a) providing a nanoporous AAO template comprising nanopores that extend down to a substrate-supported conductive layer on which the nanoporous AAO template resides;

b) filling the nanopores with nanopore filler comprising a first dielectric material to form a filled nanoporous AAO template;

c) patterning and etching the AAO template to form AAO posts;

d) conformally depositing;

(i) a dielectric layer comprising a second dielectric material, (ii) a gate metal layer, such that the dielectric and gate metal layers form a bump in the regions over the AAO posts, and (iii) a planarizable layer over the bumps that is subsequently planarized via reflow;

e) etching the dielectric, gate metal, and planarizable layers over the bump to form vias, such vias providing depositional access to the AAO posts;

f) electrochemically-depositing nanorods in the AAO posts and etching back the AAO to more fully expose the nanorods; and

g) removing the resist to form gated emitter structures.

9. The method of claim 8, wherein the step of patterning and etching the AAO template involves a lithographic patterning technique and an etching technique selected from the group consisting of dry etching, wet etching, and combinations thereof.

10. The method of claim 8, wherein the step of conformally depositing comprises deposition of a dielectric layer selected from the group consisting of SiO₂, SiN_x, epi-i-SiC, Al₂O₃, undoped wide bandgap material, and combinations thereof;

a gate metal layer selected from the group consisting of Nb, Pt, Al, W, Mo, Ti, Ni, Cr, TiW, and combinations thereof; and

a patternable layer selected from the group consisting of photoresist, UV resist, e-beam resist, and combinations thereof.

11. The method of claim 8, wherein the step of etching the dielectric, gate metal, and resist layers over the bump comprises a combination of wet and dry etching techniques.

12. The method of claim 8, wherein the step of electrochemically-depositing nanorods involves the deposition of a material selected from the group consisting of Pt, Pd, Ni, Au, Ag, Cu, Zn, ZnO, MoO₃/Mo₂O₃, and combinations thereof.

13. The method of claim 8, further comprising a step of substrate etching so as to provide for substrate posts on which the AAO posts reside.

14. A method comprising the steps of:

a) providing a nanoporous AAO template comprising nanopores that extend down to a substrate-supported conductive layer on which the nanoporous AAO template resides;

b) filling the nanopores with nanopore filler comprising a first dielectric material to form a filled nanoporous AAO template;

c) patterning and etching the AAO template to form AAO posts capped with a metal masking layer;

d) depositing a thin conformal layer of a second dielectric material over the capped AAO posts, removing residual masking layer to expose the AAO posts, electrochemically depositing nanorods in the AAO posts to form nanorod/AAO posts, and etching back the AAO to more fully expose the nanorods in the nanorod/AAO posts;

e) conformally depositing;

(i) a dielectric layer comprising a second dielectric material, (ii) a gate metal layer, such that the dielectric and gate metal layers form a bump in the regions over the nanorod/AAO posts, and (iii) a planarizable layer over the bumps that is subsequently planarized via reflow;

f) etching the dielectric, gate metal, and planarizable layers over the bump to form vias, such vias providing access to the nanorod/AAO posts; and

g) removing the planarizing layer to form gated emitter structures.

15. The method of claim 14, wherein the step-of patterning and etching the AAO template involves a lithographic patterning technique and an etching technique selected from the group consisting of dry etching, wet etching, and combinations thereof;

and wherein the metal masking layer comprises a material selected from the group consisting of Ni, Cr, Al, and combinations thereof.

16. The method of claim 14, wherein the step of electrochemically-depositing nanorods involves the deposition of a material. selected from the group consisting of Pt, Pd, Ni, Au, Ag, Cu, Zn, ZnO, MoO₃/Mo₂O₃, and combinations thereof.

17. The method of claim 14, wherein the step of conformally depositing comprises deposition of a dielectric layer selected from the group consisting of SiO₂, SiN_x, epi-i-SiC, Al₂O₃, undoped wide bandgap material, and combinations thereof;

a gate metal layer selected from the group consisting of Nb, Pt, Al, W, Mo, Ti, Ni, Cr, TiW, and combinations thereof; and

a patternable layer selected from the group consisting of photoresist, UV resist, e-beam resist, and combinations thereof.

18. The method of claim 14, wherein the step of etching the dielectric, gate metal, and resist layers over the bump comprises a combination of wet and dry etching techniques.

19. The method of claim 14, further comprising a step of substrate etching so as to provide for substrate posts on which the AAO posts reside.

20. A method comprising the steps of:

a) patterning a substrate;

b) depositing at least one Al stack, as an Al post, in a patterned microcavity region of the substrate;

c) conformally coating the Al post with layers of a dielectric material and a planarizable material;

d) etching the dielectric and planarizable layers over the post;

e) removing the planarizable and anodizing the posts to form a nanoporous AAO post on the substrate;

f) electrochemically depositing nanorods in the AAO posts to form nanorod/AAO posts;

g) conformally depositing;

(i) a dielectric layer comprising a second dielectric material, (ii) a gate metal layer, such that the dielectric and gate metal layers form a bump in the regions over the nanorod/AAO posts, and (iii) a planarizable layer over the bumps that is subsequently planarized via reflow;

h) etching the planarizable, metal, and dielectric layers over the bump to form a via exposing the nanorod/AAO posts; and

i) removing the planarizable material to form a gated emitter structure.

21. The method of claim 20, wherein the step of patterning comprises the sub-steps of:

(i) depositing a layer of dielectric on the substrate;

(ii) depositing a layer of resist on the layer of dielectric;

(iii) lithographically patterning the resist; and

(iv) etching the dielectric in regions where the resist was patterned.

22. The method of claim 20, wherein the Al stack comprises a conductive bottom layer and an Al top layer.

23. The method of claim 20, wherein the step of electrochemically-depositing nanorods involves the deposition of a material selected from the group consisting of Pt, Pd, Ni, Au, Ag, Cu, Zn, ZnO, MoO₃/Mo₂O₃, and combinations thereof.

24. The method of claim 20, wherein the step of conformally depositing comprises deposition of a dielectric layer selected from the group consisting of SiO₂, SiN_x, epi-i-SiC, Al₂O₃, undoped wide bandgap material, and combinations thereof;

a gate metal layer selected from the group consisting of Nb, Pt, Al, W, Mo, Ti, Ni, Cr, TiW, and combinations thereof; and

a resist layer selected from the group consisting of photoresist, UV resist, e-beam resist, and combinations thereof.

25. The method of claim 20, further comprising a step of substrate etching so as to provide for substrate posts on which the AAO posts reside.

26. A gated nanorod field emission device comprising:

a) a substrate;

b) a dielectric layer residing on the substrate;

c) a gate metal layer residing on top of the dielectric layer;

d) microcavities in the dielectric and gate metal layers;

e) nanoporous AAO posts residing on the substrate within the microcavities; and

f) nanorod field emitters in the nanoporous AAO posts.

27. The gated nanorod field emission device of claim 26, wherein the substrate comprises a material selected from the group consisting of. semiconductors, glasses, molecular solids, metals, ceramics, polymers, and combinations thereof.

28. The gated nanorod field emission device of claim 26, wherein the dielectric layer comprises a material selected from the group consisting of SiO₂, SiN_x, epi-i-SiC, Al₂O₃, undoped wide bandgap semiconductors, and combinations thereof;

and wherein the dielectric layer comprises a thickness of between about 100 nm and about 5 μ

m.

29. The gated nanorod field emission device of claim 26, wherein the gate metal layer comprises a material selected from the group consisting of (a) metal selected from the group consisting of Nb, Pt, Al, W, Mo, Ti, Ni, Cr, TiW, and combinations thereof;

(b) semiconductor material selected from the group consisting of highly-doped Si, GaN, GaAs, SiC, doped poly Si, doped amorphous Si, and combinations thereof; and

(c) combinations thereof; and

wherein the gate metal layer comprises a thickness of between about 10 nm and about 100 μ

m.

30. The self-aligned gated nanorod field emission device of claim 26, wherein the microcavities comprise a diameter between about 100 nm and about 5 μ

m.

31. The gated nanorod field emission device of claim 26, wherein the nanorod field emitters comprise material selected from the group consisting of Pt, Pd, Ni, Au, Ag, Cu, Zn, ZnO, MoO₃/Mo₂O₃, and combinations thereof;

and wherein the nanorod field emitters are aligned substantially perpendicular to the substrate.

32. The gated nanorod field emission device of claim 26, wherein the nanorod field emitters comprise a diameter between about 10 nm and about 500 nm;

and wherein the nanorod field emitters comprise a length between about 100 nm and about 5 μ

m.

33. The gated nanorod field emission device of claim 26, wherein the substrate further comprises a top conductive layer.

34. The gated nanorod field emission device of claim 26, wherein the substrate further comprises substrate posts.