Power sink for IC temperature control

• US 20070030019A1
• Filed: 08/04/2005
• Published: 02/08/2007
• Est. Priority Date: 08/04/2005
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kinsley, Tom
• Application Number:
  US11/196,948
• Publication Number:
  US 20070030019A1
• Time in Patent Office: Days
• US Class Current: 324/750.70
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]

Abstract

The use of a power sink function in IC testing results in a simple and rapid method for testing ICs, and assembled modules, at elevated temperature profiles without the use of environmental ovens. Testing IC devices at elevated temperatures may be useful for ‘burn-in’, for ‘hot sort’ performance testing that may be used in electronic devices such as DRAM memory, logic, communication devices, and microprocessors. The power sink function may be implemented as an additional isolated area of active devices, or as a section of the circuit that is not involved in the testing procedure. Alternately, the power dissipation circuit may consist of a resistive path between two external pins that are not used for IC operation, where the resistor may be on the IC or on the package. This allows for control of the temperature level and profile by simple adjustment of the voltage between the two external pins.

Claims

1. A method of heating a circuit, comprising:

determining a current temperature of the circuit in one of a test mode or an operational mode;

determining a desired temperature of the circuit;

enabling a power dissipation portion of the circuit at a predetermined operating rate and voltage if the desired temperature of the circuit is greater than the current temperature of the circuit; and

redetermining a new current temperature of the circuit after a predetermined time period.

2. The method of claim 1, wherein the power dissipation portion of the circuit is an additional circuit disposed in electrical isolation from a remaining portion of the circuit.

3. The method of claim 2, wherein the power dissipation portion of the circuit is disposed in a central region of the circuit.

4. The method of claim 2, wherein the power dissipation portion of the circuit further comprises a resistive element disposed electrically between at least two external contact pads not used by any other, non-power dissipation portion of the circuit.

5. The method of claim 1, wherein the power dissipation portion of the circuit comprises a portion of the circuit that is not currently being used in the circuit operation.

6. The method of claim 5, wherein the power dissipation portion of the circuit comprises a portion of the circuit that is not used in function testing of the circuit.

7. The method of claim 1, wherein the desired temperature is a burn in temperature.

8. The method of claim 1, wherein the current temperature of the circuit is obtained from a temperature sensor integrated on a same substrate as the circuit.

9. The method of claim 8, wherein the temperature sensor is a diode junction.

10. The method of claim 9, wherein the desired temperature of the circuit is not a constant temperature.

49. The method of claim 1, wherein the determining a current temperature of the circuit in an operational mode includes at least a temperature determination at a period of full operation, and the enabling the power dissipation portion of the circuit during an operational period that is less than full operation includes a desired temperature of the circuit that is equal to the temperature determination at the period of full operation.

50. The method of claim 1, wherein the determining a current temperature of the circuit in an operational mode includes at least a sleep mode, a ready mode and an operational mode, and the enabling the power dissipation portion of the circuit during at least one of the sleep mode and ready mode include a desired temperature of the circuit that is equal to the current temperature of the operational mode.

11. A method of preheating an IC circuit, comprising:

connecting the circuit to an IC tester;

determining a current temperature of the circuit in one of a test mode and an operational mode;

determining a desired temperature of the circuit;

enabling a power dissipation portion of the circuit at a predetermined operating rate and voltage if the desired temperature of the circuit is greater than the current temperature of the circuit; and

electrically testing the circuit.

12. The method of claim 11, further redetermining a new current temperature of the circuit after a predetermined time period.

13. The method of claim 11, wherein the power dissipation portion of the circuit is an additional circuit disposed in electrical isolation from a remaining portion of the circuit.

14. The method of claim 13, wherein the power dissipation circuit further comprises a resistive element disposed electrically between at least two external contact pads not used by any portion of the circuit.

15. The method of claim 14, wherein the resistive element is located on an IC package containing the IC circuit using two of the package leads not used by the IC circuit, and in thermal contact with at least a portion of the IC.

16. The method of claim 13, wherein the additional circuit comprises a plurality of electrically connected circuits that are disposed in a predetermined pattern to be evenly distributed around the circuit.

17. The method of claim 11, wherein the desired temperature is a burn in temperature.

18. The method of claim 11, wherein the current temperature of the circuit is obtained from a temperature sensor integrated on the same substrate as the circuit.

19. The method of claim 18, wherein the temperature sensor is a diode junction.

20. The method of claim 19, wherein the desired temperature of the circuit is not a constant temperature.

21. A method of testing an electronic circuit, comprising:

connecting an assembled printed circuit board including a plurality of integrated circuits to an electronic tester;

determining a current temperature of selected individual ones of the plurality of integrated circuits in one of a test mode and an operational mode;

determining a desired temperature of each one of the selected individual ones of the plurality of integrated circuits;

enabling a power dissipation portion of each one of the selected individual ones of the plurality of integrated circuits if the desired temperature of the selected individual one of the plurality of integrated circuits is greater than the current temperature of the selected individual one of the plurality of integrated circuits; and

electrically testing the electronic circuit.

22. The method of claim 21, further redetermining a new current temperature of each selected individual one of the plurality of integrated circuits after a predetermined time period.

23. The method of claim 21, wherein the power dissipation portion of each of the integrated circuits is an additional circuit disposed in electrical isolation from a remaining portion of the integrated circuit.

24. The method of claim 23, wherein the additional circuit further comprises a resistive element disposed electrically between two external contact pads.

25. The method of claim 23, wherein the additional circuit comprises a portion of the integrated circuit that is not currently being used in the test operation.

26. The method of claim 23, wherein the additional circuit comprises a plurality of electrically connected circuits that are disposed in a predetermined pattern to be evenly distributed around the circuit.

27. The method of claim 21, wherein the desired temperature is one of a hot sort test temperature, a room temperature, and an accelerated life test temperature.

28. The method of claim 21, wherein the current temperature of the circuit is obtained from a temperature sensor on selected ones of the plurality of integrated circuits.

29. The method of claim 28, wherein the temperature sensor is a diode junction.

30. The method of claim 29, wherein the desired temperature of the circuit is not a constant temperature.

31. A method of operating an electronic device, comprising:

determining a current temperature of a preselected circuit in the electronic device in one of a test mode and an operational mode;

determining a desired temperature of the preselected circuit;

enabling a power dissipation portion of the preselected circuit for a fixed time period if the desired temperature of the circuit is greater than the current temperature of the circuit; and

redetermining a new current temperature of the circuit at the end of the fixed time period.

32. The method of claim 31, wherein the power dissipation portion of the circuit is an additional circuit disposed in electrical isolation from a remaining portion of the circuit.

33. The method of claim 32, wherein the power dissipation portion of the circuit further comprises a resistive element disposed electrically between two external contact pads.

34. The method of claim 31, wherein the current temperature of the preselected circuit is obtained from a temperature sensor integrated on the circuit.

35. The method of claim 34, wherein the temperature sensor is a diode junction.

36. The method of claim 31, wherein the desired temperature of the circuit is not a constant temperature.

37-40. -40. (canceled)

41. A method of operating an electronic device, comprising:

determining a current temperature of the electronic device in one of a test mode and an operational mode;

enabling a power dissipation circuit for a fixed time period if a desired temperature of the circuit is greater than the current temperature of the circuit; and

redetermining a new current temperature at the end of the fixed time period.

42. The method of claim 41, wherein enabling the power dissipation circuit includes a command sequence to a mode register having at least an enable bit and at least two selection bits to enable a selected one of at least four power dissipation circuits, each having different power dissipation levels.

43. The method of claim 42, wherein the four power dissipation circuits are low impedance circuits and have equivalent resistance levels of one of 100, 200, 300 and 400 Ohms respectively, and any set of four unique resistance values.

44. The method of claim 42, wherein the four power dissipation circuits are low impedance circuits and have a design similar to on die termination circuitry.

45. The method of claim 42, wherein the four power dissipation circuits are controlled by the mode register to use combinations of the die termination circuitry that are not currently selected.

46. The method of claim 41, wherein the electronic device is a DRAM and the power dissipation circuit is enabled prior to a functional test operation.

47. The method of claim 41, wherein the power dissipation circuit is toggled by a signal on an external device pin not used by any other circuit function.

48. The method of claim 46, wherein the DRAM is a DDR2 SDRAM having a plurality of on die termination circuits controlled by a mode register.