Power sink for IC temperature control

• US 20070030020A1
• Filed: 07/28/2006
• Published: 02/08/2007
• Est. Priority Date: 08/04/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kinsley, Tom
• Granted Patent: US 8,030,952 B2
• Time in Patent Office: Days
• US Class Current: 324/750.30
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]

Abstract

The use of a power sink function in IC testing results in a simple and rapid method for testing ICs, and assembled modules, at elevated temperature profiles without the use of environmental ovens. Testing IC devices at elevated temperatures may be useful for ‘burn-in’, for ‘hot sort’ performance testing that may be used in electronic devices such as DRAM memory, logic, communication devices, and microprocessors. The power sink function may be implemented as an additional isolated area of active devices, or as a section of the circuit that is not involved in the testing procedure. Alternately, the power dissipation circuit may consist of a resistive path between two external pins that are not used for IC operation, where the resistor may be on the IC or on the package. This allows for control of the temperature level and profile by simple adjustment of the voltage between the two external pins.

Claims

1. An electronic device, comprising:

a semiconductor substrate having a plurality of semiconductor devices forming a functional circuit;

an integrated temperature sensor integrated on the semiconductor substrate;

a power dissipation circuit formed on the substrate in electrical isolation from the circuit;

a comparator for comparing an output of the integrated temperature sensor with a desired temperature value; and

a timer circuit electrically connected to the power dissipation circuit and the comparator for enabling the power dissipation circuit for a predetermined time period if the comparator shows the output of the integrated temperature sensor being lower than the desired temperature value.

2. The device of claim 1, wherein the desired temperature value is stored in a memory formed in the electronic device.

3. The device of claim 1, wherein the desired temperature value is an externally input value to the comparator from an input/output connection.

4. The device of claim 1, wherein after the predetermined time period expires, the comparator again compares the output of the integrated sensor to the desired temperature value.

5. An electronic device, comprising:

a plurality of devices and an integrated temperature sensor on a semiconductor substrate;

a power dissipation circuit on the substrate in electrical isolation from the devices;

a comparator connected to the integrated temperature sensor and to a desired temperature value; and

a timer circuit connected to the power dissipation circuit.

6. The device of claim 5, wherein the timer circuit is electrically connected to a power supply, the power dissipation circuit, and the comparator, and enables the power supply to the power dissipation circuit for a predetermined time period when the comparator shows an output of the integrated temperature sensor lower than the desired temperature value.

7. The device of claim 6, wherein after the predetermined time period expires, the comparator again compares the output of the integrated sensor to the desired temperature value.

8. The device of claim 6, wherein the desired temperature value is stored in a memory circuit location in the electronic device.

9. The device of claim 6, wherein the desired temperature value is an external input value to the comparator from an input/output connection.

10. The device of claim 8, wherein the predetermined time period is stored in a memory circuit location in the electronic device.

11. The device of claim 5, wherein the power dissipation circuit on the substrate in electrical isolation from the devices is comprises individual ones of the plurality of devices not used in a functional circuit operation of the electronic device.

12. The device of claim 11, wherein the power dissipation circuit can be enabled during at least one of the normal operation of the functional circuit, a test operation of the functional circuit, a reliability test operation, a burn-in operation and a pre-heat period prior to normal operation of the functional circuit.

13. The device of claim 11, wherein the power dissipation circuit is in a central region of the semiconductor substrate.

14. The device of claim 11, wherein the power dissipation circuit comprises individual devices remotely located from one another in a plurality of peripheral and central regions of the semiconductor substrate.

15. The device of claim 11, wherein the power dissipation circuit is distributed substantially equally in all regions of the semiconductor substrate.

16. A device, comprising:

a functional circuit comprising a plurality of semiconductor devices on a semiconductor substrate;

an integrated temperature sensor on the semiconductor substrate;

a power dissipation circuit on the substrate;

a comparator comparing an output of the integrated temperature sensor with a desired temperature value; and

a timer circuit electrically connected to the power dissipation circuit and the comparator enabling the power dissipation circuit for a predetermined time period when the comparator measures the output of the integrated temperature sensor lower than the desired temperature value.

17. The device of claim 16, wherein the power dissipation circuit comprises an additional circuit electrically isolated from the functional circuit.

18. The device of claim 16, wherein the power dissipation circuit comprises a portion of the functional circuit not currently in an operational mode.

19. The device of claim 17, wherein the power dissipation portion of the circuit is located in a central region of the circuit.

20. The method of claim 19, wherein the power dissipation circuit further comprises a resistive element disposed electrically between at least two external contact pads not used by any other, non-power dissipation portion of the circuit.

21. The device of claim 16, wherein the power dissipation portion of the circuit comprises a portion of the plurality of devices not currently being used in the functional circuit operation.

22. The device of claim 21, wherein the power dissipation portion of the circuit comprises a portion of the circuit that is not used in function testing of the circuit.

23. The device of claim 16, wherein the desired temperature is a burn in temperature provided by an external voltage on an input pad.

24. The device of claim 16, wherein the integrated temperature sensor on the semiconductor substrate comprises at least one of the plurality of semiconductor devices.

25. The device of claim 24, wherein the temperature sensor comprises a diode junction.

26. The device of claim 17, wherein the additional circuit comprises a plurality of electrically connected circuits that are disposed in a predetermined pattern to be evenly distributed around the circuit.

27. The device of claim 16, wherein enabling the power dissipation circuit includes a command sequence to a mode register having at least an enable bit and at least two selection bits to enable a selected one of at least four power dissipation circuits, each having different power dissipation levels.

28. The device of claim 27, wherein the four power dissipation circuits comprise low impedance circuits and have equivalent resistance levels of at least one of 100, 200, 300 and 400 Ohms respectively, and any set of four unique resistance values.

29. The device of claim 27, wherein the four power dissipation circuits comprises at least one of low impedance circuitry and on die termination circuitry.

30. The device of claim 29, wherein the four power dissipation circuits are controllable by the mode register to use combinations of the die termination circuitry that are not currently selected.

31. The device of claim 16, wherein the device is a DRAM and the power dissipation circuit is enabled prior to a functional test operation.

32. The device of claim 16, wherein the power dissipation circuit is toggled by a signal on an external device pin not used by any other circuit function.

33. The device of claim 31, wherein the DRAM is a DDR2 SDRAM having a plurality of on die termination circuits controlled by a mode register.