Interconnection and input/output resources for programmable logic integrated circuit devices

• US 20070030029A1
• Filed: 11/07/2005
• Published: 02/08/2007
• Est. Priority Date: 03/04/1999
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Schleicher, James, Pedersen, Bruce, Patel, Rakesh, Shumarayev, Sergey, Huang, Wei-Jen, Ngai, Tony, Maruri, Victor
• Granted Patent: US 7,317,332 B2
• Time in Patent Office: Days
• US Class Current: 326/41
• CPC Class Codes: G06F 7/506 with simultaneous carry generation for, or propagation over, two or more stages
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1774 for global signals, e.g. clock, reset
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/17792 for operating speed

Abstract

A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

Claims

1-47. -47. (canceled)

48. A programmable logic integrated circuit device comprising:

a plurality of logic regions arranged in a multi-dimensional array; and

a plurality of input/output cells located within the multi-dimensional array.

49. The device of claim 48, wherein at least a portion of the cells are arranged in a predetermined pattern.

50. The device of claim 49, wherein the predetermined pattern is a multi-dimensional array of cells spanning at least a portion of the device.

51. The device of claim 48, further comprising:

a plurality of conductors extending adjacent to the cells and logic regions; and

a plurality of programmable logic connectors operative to apply signals from the cells and logic regions to the conductors.

52. The device of claim 48, further comprising:

a plurality of conductors extending adjacent to the cells and logic regions; and

a plurality of programmable logic connectors operative to apply signals from the conductors to the cells and logic regions.

53. The device of claim 48, further comprising:

a plurality of conductors extending adjacent to the cells and logic regions; and

a plurality of I/O signal communication regions located within the multi-dimensional array and operative to supply signals received by the I/O signal communication regions to the conductors.

54. The device of claim 48, wherein at least some of the I/O cells include I/O signal communication regions.

55. The device of claim 48, further comprising:

signal communication regions disposed within the multi-dimensional array of logic regions in a center portion of the device.

56. The device of claim 55, wherein the signal communication regions receive clock signals.

57. The device of claim 48, wherein at least one of the I/O cells is disposed in a center portion of the device.

58. A programmable logic integrated circuit device, comprising:

a plurality of logic regions arranged in predetermined groups of the logic regions; and

a plurality of I/O regions disposed between the predetermined groups of logic regions.

59. The device of claim 58, wherein at least some of the I/O regions include I/O signal communication regions for transmitting and/or receiving signals.

60. The device of claim 58, further comprising:

signal communication regions disposed between the predetermined groups of logic regions in a center portion of the device.

61. The device of claim 60, wherein the signal communication regions receive clock signals.

62. The device of claim 60, wherein the signal communication regions receive input signals.

63. The device of claim 60, further comprising:

a plurality of conductors coupled to the signal communication regions.

64. The device of claim 63, wherein the conductors are operative to convey signals to the logic regions and the I/O regions.

65. The device of claim 58, wherein a predetermined group of logic regions includes a column of logic regions.

66. The device of claim 65, wherein a portion of the I/O regions is disposed as a column of I/O regions between columns of logic regions.