Delay circuit and delay synchronization loop device

• US 20070030040A1
• Filed: 10/13/2006
• Published: 02/08/2007
• Est. Priority Date: 07/31/2003
• Status: Active Grant

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Takai, Yasuhiro, Kobayashi, Shotaro
• Granted Patent: US 7,348,823 B2
• Time in Patent Office: Days
• US Class Current: 327/156
• CPC Class Codes: H03K 2005/00058 controlled by a digital setting
• CPC Class Codes: H03K 2005/00241 using shift registers
• CPC Class Codes: H03K 2005/00247 using counters
• CPC Class Codes: H03K 2005/00273 using digital comparators
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals
• CPC Class Codes: H03L 7/0818 the controlled phase shifter comprising coarse and fine delay or phase-shifting means
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop

Abstract

A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

Claims

1. A clock generator comprising:

a circuit for receiving an input clock signal;

a circuit for generating an internal clock signal synchronized with the input clock signal; and

a control circuit for switching between a first mode of generating the rising edge of said internal clock signal, from the rising edge of said input clock signal, and generating the falling edge of said internal clock signal, from the falling edge of said input clock signal, based on a switching control signal, and a second mode of generating the falling edge of said internal clock signal, from the rising edge of said input clock signal, and generating the rising edge of the internal clock signal from the falling edge of said input clock signal, based on said switching control signal.

2. The clock generator of claim 1, wherein the circuit for generating an internal clock signal synchronized with the input clock signal comprises:

a circuit for calculating a difference between a phase of the input clock signal and a phase of the internal clock signal and generating a phase comparison signal based on the calculated phase difference;

a circuit for generating a delay control signal based on the phase comparison signal and setting a delay time for a delay line;

a delay line for outputting a rising edge and a falling edge of a clock signal based on the phase comparison signal; and

a multiplexer circuit for generating the internal clock signal based on the switching control signal.

3. The clock generator of claim 1, wherein the control circuit comprises:

a mode decision circuit for outputting the switching control signal;

a selector for outputting a first and second phase comparison signals based on the switching control signal;

4. The clock generator of claim 3, wherein the mode decision circuit is controlled by the phase comparison signal;

5. The clock generator of claim 3, wherein the selector comprises:

a first and a second multiplexer controlled by the mode selector circuit wherein each multiplexer includes;

a first and second input terminal for receiving the first and second phase comparison signals, and

an output terminal for outputting the first and second phase comparison signals based on the switching control signal.

6. The clock generator of claim 3, wherein the mode decision circuit comprises:

a D-type flip-flop having a first and second input terminal for receiving a control signal and an output terminal for outputting the switching control signal.

7. The clock generator of claim 3, wherein the multiplexer circuit comprises:

a first and second multiplexer controlled by the switching control signal, wherein each multiplexer includes a first and second input for receiving a delayed output of the selector, and

a SR flip-flop for outputting the internal clock signal having a set terminal connected to the output of the first multiplexer and a reset terminal connected to the output of the second multiplexer.

8. The clock generator of claim 1, wherein the control circuit comprises:

a mode decision circuit for outputting a switching control signal;

a dummy circuit for adjusting the internal clock signal based on the switching control signal and outputting a clock feedback signal; and

a first and second phase detection circuit for generating a phase comparison result signal based on the switching control signal.

9. The clock generator of claim 8, wherein the first phase detector circuit comprises:

a phase detector for receiving the input clock signal and the internal clock signal and outputting complementary phase comparison signals, and

a multiplexer for selecting the output signal of the phase detector based on the switching control signal.

10. The clock generator of claim 8, wherein the second phase detector circuit comprises:

a phase detector for receiving the input clock signal and an inverted internal clock signal and outputting complementary phase comparison signals, and

a multiplexer for selecting the output signal of the phase detector based on the switching control signal.

11. The clock generator of claim 8, wherein the dummy circuit comprises:

a buffer circuit for generating a rise and fall signal based on the internal clock signal and outputting the internal clock signal and a complementary signal, and

a multiplexer for selecting between the internal clock signal and the complementary signal based on the switching control signal.

12. A method for setting a rising edge of an internal clock signal independent of a falling edge of the internal clock signal clock signal in a clock signal generating circuit, comprising:

receiving an input clock signal;

generating a first phase comparison signal based on a phase difference between a rising edge of the input clock signal and a rising edge of an internal clock signal and a second phase comparison signal based on the phase difference between a falling edge of the input clock signal and a falling edge of the internal clock signal;

determining an operating mode for the clock signal generating circuit;

determining an output order of the phase comparison signals based on the operating mode; and

generating the internal clock signal based on the phase comparison signals and the operating mode.