Delay circuit and delay synchronization loop device
First Claim
1. A clock generator comprising:
- a circuit for receiving an input clock signal;
a circuit for generating an internal clock signal synchronized with the input clock signal; and
a control circuit for switching between a first mode of generating the rising edge of said internal clock signal, from the rising edge of said input clock signal, and generating the falling edge of said internal clock signal, from the falling edge of said input clock signal, based on a switching control signal, and a second mode of generating the falling edge of said internal clock signal, from the rising edge of said input clock signal, and generating the rising edge of the internal clock signal from the falling edge of said input clock signal, based on said switching control signal.
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Accused Products
Abstract
A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.
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Citations
12 Claims
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1. A clock generator comprising:
- a circuit for receiving an input clock signal;
a circuit for generating an internal clock signal synchronized with the input clock signal; and
a control circuit for switching between a first mode of generating the rising edge of said internal clock signal, from the rising edge of said input clock signal, and generating the falling edge of said internal clock signal, from the falling edge of said input clock signal, based on a switching control signal, and a second mode of generating the falling edge of said internal clock signal, from the rising edge of said input clock signal, and generating the rising edge of the internal clock signal from the falling edge of said input clock signal, based on said switching control signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
- a circuit for receiving an input clock signal;
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12. A method for setting a rising edge of an internal clock signal independent of a falling edge of the internal clock signal clock signal in a clock signal generating circuit, comprising:
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receiving an input clock signal;
generating a first phase comparison signal based on a phase difference between a rising edge of the input clock signal and a rising edge of an internal clock signal and a second phase comparison signal based on the phase difference between a falling edge of the input clock signal and a falling edge of the internal clock signal;
determining an operating mode for the clock signal generating circuit;
determining an output order of the phase comparison signals based on the operating mode; and
generating the internal clock signal based on the phase comparison signals and the operating mode.
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Specification